Low power consumption semiconductor integrated circuit device and microprocessor

Claim 2

A semiconductor integrated circuit device comprising: a memory; a decoder for decoding an instruction, wherein said decoder comprises: a detector for detecting whether or not said instruction is instructing an accessing of said memory, and a signal generator responsive to an accessing determination by said detector for generating a memory access previous notice signal prior to an initiation of operations for accessing said memory when said instruction is instructing an accessing of said memory; an activator responsive to said memory access previous notice signal for activating said memory from a low power mode to a normal operation mode prior to said initiation of operations for accessing said memory.

Claim 3

A semiconductor integrated circuit device according to claim 1 wherein said detector detects a LOAD/STORE instruction.

Claim 4

A semiconductor integrated circuit as claimed in claim 1, further comprising an address generator for generating a memory address for accessing said memory according to said decoded instruction.

Claim 5

A semiconductor integrated circuit device as claimed in claim 1, wherein said activator additionally is for deactivating said memory from a normal operation mode to a low power mode after completion of operations for accessing said memory.

Claim 6

A microprocessor comprising: a register for storing an instruction; a decoder for decoding said instruction held in said resister; an arithmetic and logic operation unit for executing instructions; register file connected to said arithmetic and logic operation unit for storing data; wherein said decoder comprises: a detector for detecting whether or not said instruction is one of an instruction which instructs: A.) an execution operation in said arithmetic and logic operation unit and, B.) an accessing of said register file; and a signal generator responsive to a detecting determination by said detector for generating one of: A.) an operation previous notice signal and. B.) a register access previous notice signal; an activator responsive to said one of an operation previous notice signal and register access previous notice signal for activating one of said arithmetic and logic operation unit and said register file from a low power mode to a normal operation mode prior to an accessing of one of said arithmetic and logic operation circuit and said register file.

Claim 7

A microprocessor comprising: a register for storing an instruction; a decoder for decoding said instruction held in said resister; an arithmetic and logic operation unit for executing instructions; register file connected to said arithmetic and logic operation unit for storing data; wherein said decoder comprises: a detector for detecting whether or not said instruction is one of an instruction which instructs: A.) an execution operation in said arithmetic and logic operation unit and, B.) an accessing of said register file; and a signal generator responsive to a detecting determination by said detector for generating one of: A.) an operation previous notice signal and. B.) a register access previous notice signal; an activator responsive to said one of an operation previous notice signal and register access previous notice signal for activating one of said arithmetic and logic operation unit and said register file from a low power mode to a normal operation mode prior to an accessing of one of said arithmetic and logic operation circuit and said register file.

Claim 8

A microprocessor according to claim 5 wherein said decoder generates said register access previous notice signal at least one accessing time period prior to an accessing of said register file.

Claim 9

A microprocessor according to claim 5 wherein said activator increases an operation current of said one of said arithmetic and logic operation unit and said register file at a predetermined change rate from a current level smaller than a predetermined operating current level to said predetermined operating current level from the time of occurrence of one of said operation previous notice signal and said register access previous notice signal to the time of an actual access of one of said arithmetic and logic operation unit and said register file.

Claim 10

A microprocessor as claimed in claim 5, wherein said activator additionally is for deactivating said one of said arithmetic and logic operation unit and said register file from a normal operation mode to a low power mode after an accessing of said one of said arithmetic and logic operation unit and said register file.

Claim 11

A microprocessor comprising: at least one functional circuit block; an instruction decoder for decoding an instruction and outputting an execution signal for instructing the execution of said instruction by selected functional circuit blocks of said at least one functional circuit block; a signal generator for detecting said execution signal prior to the initiation of operations for execution by said selected functional circuit blocks when said instruction is instructing an execution by said selected functional circuit blocks and for supplying an operation previous notice signal with respect to said selected functional circuit blocks for which the execution has been detected; and an activator responsive to said operation previous notice signal for activating said selected functional circuit blocks from a low power mode to a normal, operation mode prior to said initiation of operations for execution by said selected functional circuit blocks.

Claim 12

A microprocessor comprising: at least one functional circuit block; an instruction decoder for decoding an instruction and outputting an execution signal for instructing the execution of said instruction by selected functional circuit blocks of said at least one functional circuit block; a signal generator for detecting said execution signal prior to the initiation of operations for execution by said selected functional circuit blocks when said instruction is instructing an execution by said selected functional circuit blocks and for supplying an operation previous notice signal with respect to said selected functional circuit blocks for which the execution has been detected; and an activator responsive to said operation previous notice signal for activating said selected functional circuit blocks from a low power mode to a normal, operation mode prior to said initiation of operations for execution by said selected functional circuit blocks.

Claim 13

A microprocessor as claimed in claim 9, wherein said activator additionally is for deactivating said selected functional circuit blocks from a normal operation mode to a low power mode after completion of operations for execution by said selected functional circuit blocks.

Claim 14

A semiconductor integrated circuit device comprising: a memory; a decoder for decoding an instruction, wherein said decoder comprises: a detector for detecting whether or not said instruction is instructing an accessing of said memory, and a signal generator responsive to an accessing determination by said detector for generating a memory access previous notice signal prior to an accessing of said memory; an activator responsive to said memory access previous notice signal for activating said memory from a low power mode to a normal operation mode prior to an accessing of said memory, and wherein said memory is a clock synchronized memory.

Claim 15

A semiconductor integrated circuit device comprising: a memory; a decoder for decoding an instruction, wherein said decoder comprises: a detector for detecting whether or not said instruction is instructing an accessing of said memory, and a signal generator responsive to an accessing determination by said detector for generating a memory access previous notice signal prior to an accessing of said memory; an activator responsive to said memory access previous notice signal for activating said memory from a low power mode to a normal operation mode prior to an accessing of said memory, and wherein said memory is a clock synchronized memory.

Claim 16

A semiconductor integrated circuit device according to claim 11 further comprising: a clock generator for generating a memory access clock signal based on a system clock signal of the semiconductor integrated circuit device and said access previous notice signal.

Claim 17

A semiconductor integrated circuit device according to claim 14 further comprising: a pulse generator for generating a pulse for activating a sense amplifier of said memory based on a system clock signal of the semiconductor integrated circuit device and said access previous notice signal.

Claim 18

A semiconductor integrated circuit device comprising: a memory; a decoder for decoding an instruction, wherein said decoder comprises: a detector for detecting whether or not said instruction is instructing an accessing of said memory, and a signal generator responsive to an accessing determination by said detector for generating a memory access previous notice signal prior to initiation of operations for accessing said memory when said instruction is instructing an accessing of said memory; an activator responsive to said memory access previous notice signal for activating said memory from a low power mode to a normal operation mode prior to said initiation of operations for accessing of said memory, said activating being initiated a predetermined time prior to said initiation of operations for accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a memory operation of said memory.

Claim 19

A semiconductor integrated circuit device comprising: a memory; a decoder for decoding an instruction, wherein said decoder comprises: a detector for detecting whether or not said instruction is instructing an accessing of said memory, and a signal generator responsive to an accessing determination by said detector for generating a memory access previous notice signal prior to initiation of operations for accessing said memory when said instruction is instructing an accessing of said memory; an activator responsive to said memory access previous notice signal for activating said memory from a low power mode to a normal operation mode prior to said initiation of operations for accessing of said memory, said activating being initiated a predetermined time prior to said initiation of operations for accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a memory operation of said memory.

Claim 20

A semiconductor integrated circuit device comprising: a memory; a decoder for decoding an instruction, wherein said decoder comprises: a detector for detecting whether or not said instruction is instructing an accessing of said memory, and a signal generator responsive to an accessing determination by said detector for generating a memory access previous notice signal prior to an accessing of said memory; an activator responsive to said memory access previous notice signal for activating said memory from a low power mode to a normal operation mode prior to an accessing of said memory, said activating being initiated a predetermined time prior to said accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a memory operation of said memory; wherein said activator additionally is for deactivating said memory from a normal operation mode to a low power mode after an accessing of said memory, said deactivating being initiated a predetermined time after said accessing so as to prevent any noise signals resultant from a normal-operation-power-to-low-power transition from affecting said memory operation of said memory.

Claim 21

A semiconductor integrated circuit device comprising: a memory; a decoder for decoding an instruction, wherein said decoder comprises: a detector for detecting whether or not said instruction is instructing an accessing of said memory, and a signal generator responsive to an accessing determination by said detector for generating a memory access previous notice signal prior to an accessing of said memory; an activator responsive to said memory access previous notice signal for activating said memory from a low power mode to a normal operation mode prior to an accessing of said memory, said activating being initiated a predetermined time prior to said accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a memory operation of said memory; wherein said activator additionally is for deactivating said memory from a normal operation mode to a low power mode after an accessing of said memory, said deactivating being initiated a predetermined time after said accessing so as to prevent any noise signals resultant from a normal-operation-power-to-low-power transition from affecting said memory operation of said memory.

Claim 22

A microprocessor comprising; a register for storing an instruction; a decoder for decoding said instruction held in said resister; an arithmetic and logic operation unit for executing instructions; register file connected to said arithmetic and logic operation unit for storing data; wherein said decoder comprises: a detector for detecting whether or not said instruction is one of an instruction which instructs: A.) an execution operation in said arithmetic and logic operation unit and, B.) an accessing of said register file; and a signal generator responsive to a detecting determination by said detector for generating one of: A.) an operation previous notice signal and, B.) a register access previous notice signal; an activator responsive to said one of an operation previous notice signal and register access previous notice signal for activating one of said arithmetic and logic operation unit and said register file from a low power mode to a normal operation mode prior to an accessing of one of said arithmetic and logic operation unit and said register file, said activating being initiated a predetermined time prior to said accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect an operation of said arithmetic and logic operation unit and said register file.

Claim 23

A microprocessor comprising; a register for storing an instruction; a decoder for decoding said instruction held in said resister; an arithmetic and logic operation unit for executing instructions; register file connected to said arithmetic and logic operation unit for storing data; wherein said decoder comprises: a detector for detecting whether or not said instruction is one of an instruction which instructs: A.) an execution operation in said arithmetic and logic operation unit and, B.) an accessing of said register file; and a signal generator responsive to a detecting determination by said detector for generating one of: A.) an operation previous notice signal and, B.) a register access previous notice signal; an activator responsive to said one of an operation previous notice signal and register access previous notice signal for activating one of said arithmetic and logic operation unit and said register file from a low power mode to a normal operation mode prior to an accessing of one of said arithmetic and logic operation unit and said register file, said activating being initiated a predetermined time prior to said accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect an operation of said arithmetic and logic operation unit and said register file.

Claim 24

A microprocessor as claimed in claim 16, wherein said activator additionally is for deactivating said one of said arithmetic and logic operation unit and said register file from a normal operation mode to a low power mode after an accessing of one of said arithmetic and logic operation unit and said register file, said deactivating being initiated a predetermined time after said accessing so as to prevent any noise signals resultant from a normal-operation-power-to-low-power transition from affecting an accessing of said one of said arithmetic and logic operation unit and said register file.

Claim 25

A microprocessor comprising: at least one functional circuit block; an instruction decoder for decoding an instruction and outputting an execution signal for instructing the execution of said instruction by selected functional circuit blocks of said at least one functional circuit block; a signal generator for detecting said execution signal prior to the initiation of operations for execution by said selected functional circuit blocks and for supplying an operation previous notice signal with respect to said selected functional circuit blocks for which the execution has been detected; and an activator responsive to said operation previous notice signal for activating said selected functional circuit blocks from a low power mode to a normal operation mode prior to said initiation of operations for execution by said selected functional circuit blocks, said activating being initiated a predetermined time prior to said initiation of operation for execution so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a functional operation of said selected functional circuit blocks.

Claim 26

A microprocessor comprising: at least one functional circuit block; an instruction decoder for decoding an instruction and outputting an execution signal for instructing the execution of said instruction by selected functional circuit blocks of said at least one functional circuit block; a signal generator for detecting said execution signal prior to the initiation of operations for execution by said selected functional circuit blocks and for supplying an operation previous notice signal with respect to said selected functional circuit blocks for which the execution has been detected; and an activator responsive to said operation previous notice signal for activating said selected functional circuit blocks from a low power mode to a normal operation mode prior to said initiation of operations for execution by said selected functional circuit blocks, said activating being initiated a predetermined time prior to said initiation of operation for execution so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a functional operation of said selected functional circuit blocks.

Claim 27

A microprocessor comprising: at least one functional circuit block; an instruction decoder for decoding an instruction and outputting an execution signal for instructing the execution of said instruction by selected ones of said at least one functional circuit block; a signal generator for detecting said execution signal prior to the start of execution by a functional circuit block and for supplying an operation previous notice signal with respect to selected functional circuit blocks for which the execution has been detected; and an activator responsive to said operation previous notice signal for activating said selected functional circuit blocks from a low power mode to a normal operation mode prior to an execution of said instruction by said functional circuit block, said activating being initiated a predetermined time prior to said accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a functional operation of said selected functional circuit blocks, wherein said activator additionally is for deactivating said functional circuit block from a normal operation mode to a low power mode after said execution by said functional circuit block, said deactivating being initiated a predetermined time after said execution so as to prevent any noise signals resultant from a normal-operation-power-to-low-power-transition from affecting said execution by said functional circuit block.

Claim 28

A microprocessor comprising: at least one functional circuit block; an instruction decoder for decoding an instruction and outputting an execution signal for instructing the execution of said instruction by selected ones of said at least one functional circuit block; a signal generator for detecting said execution signal prior to the start of execution by a functional circuit block and for supplying an operation previous notice signal with respect to selected functional circuit blocks for which the execution has been detected; and an activator responsive to said operation previous notice signal for activating said selected functional circuit blocks from a low power mode to a normal operation mode prior to an execution of said instruction by said functional circuit block, said activating being initiated a predetermined time prior to said accessing so as to allow any noise signals resultant from a low-power-to-normal-operation-power transition to subside to at least a level where said noise signals will not affect a functional operation of said selected functional circuit blocks, wherein said activator additionally is for deactivating said functional circuit block from a normal operation mode to a low power mode after said execution by said functional circuit block, said deactivating being initiated a predetermined time after said execution so as to prevent any noise signals resultant from a normal-operation-power-to-low-power-transition from affecting said execution by said functional circuit block.