Field programmable digital signal processing array integrated circuit

Claim 2

A field programmable, digital signal processing integrated circuit, comprising: a plurality of input/output pads; at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs; at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output; a plurality of ALU (arithmetic logic units) circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines; means for individually defining the operation to be performed by each of said ALU circuits; a plurality of interconnect conductors in the integrated circuit; interconnect means for making programmable connections between the interconnect conductors, said inputs and outputs of said ALU circuits, said digital inputs and outputs of said at least one analog to digital converter, said digital inputs and outputs of said at least one digital to analog converter, and said input/output pads, at least some of said interconnect means being user programmable; the n output lines of at least one of said ALU circuits intersecting n interconnect conductors to form intersections, said n interconnect conductors connectable to the input lines of other ones of said ALU circuits; user-programmable interconnect elements disposed at said intersections; and means for programming ones of said user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said n output lines of said at least one of said ALU circuits and said n interconnect conductors, whereby multiplication and division operations may be performed on said data by virtue of programmable interconnection.

Claim 3

The field programmable, digital signal processing integrated circuit of claim 1, further including: at least one PROM circuit disposed in said integrated circuit, said PROM including a plurality of address input lines and a plurality of data output lines; interconnect means for connecting ones of said interconnect conductors to said plurality of address input lines and said plurality of data output lines of said at least one PROM circuit.

Claim 4

A field programmable, digital signal processing integrated circuit, comprising: a plurality of input/output pads; at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs; at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output; a plurality of ALU circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines; means for individually defining the operation to be performed by each of said ALU circuits; a plurality of interconnect conductors in the integrated circuit; the n input lines of either of said first and second input bus of at least one of said ALU circuits intersecting n interconnect conductors in sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form intersections; user-programmable interconnect elements disposed at said intersections; and means for programming ones of said user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said n interconnect conductors and on said n input lines of either of said first and second input bus of at said least one of said ALU circuits and, whereby multiplication and division operations may be performed on said data by virtue of interconnection.

Claim 5

A field programmable, digital signal processing integrated circuit, comprising: a plurality of input/output pads; at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs; at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output; a plurality of ALU circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines; means for individually defining the operation to be performed by each of said ALU circuits; a plurality of interconnect conductors in the integrated circuit; the n input lines of either of said first and second input bus of at least one of said ALU circuits intersecting n interconnect conductors in sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form intersections; user-programmable interconnect elements disposed at said intersections; and means for programming ones of said user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between data on said n interconnect conductors and on said n input lines of either of said first and second input bus of at said least one of said ALU circuits and, whereby multiplication and division operations may be performed on said data by virtue of interconnection.

Claim 6

A field programmable, digital signal processing integrated circuit, comprising: a plurality of input/output pads; at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs; at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output; a plurality of ALU circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines; means for individually defining the operation to be performed by each of said ALU circuits; a plurality of interconnect conductors in the integrated circuit; interconnect means for making programmable connections between the interconnect conductors, said inputs and outputs of said ALU circuits, said digital inputs and outputs of said at least one analog to digital converter, said digital inputs and outputs of said at least one digital to analog converter, and said input/output pads, at least some of said interconnect means comprising user-programmable interconnect elements; said n input lines of the first input bus of at least one of said ALU circuits intersecting n interconnect conductors in first sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form first intersections; first user-programmable interconnect elements disposed at said first intersections; means for programming ones of said first user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between first data on said n interconnect conductors of said first sets of said interconnect conductors and the n input lines of the first input bus of said at least one of said ALU circuits, whereby multiplication and division operations may be performed on said first data by virtue of interconnection.

Claim 7

A field programmable, digital signal processing integrated circuit, comprising: a plurality of input/output pads; at least one analog to digital converter disposed in said integrated circuit, said at least one analog to digital converter having an analog input and a plurality of digital outputs; at least one digital to analog converter disposed in said integrated circuit, said at least one digital to analog converter having a plurality of digital inputs and an analog output; a plurality of ALU circuits disposed in the integrated circuit, each of said ALU circuits having a first input bus for supplying a first n-bit input byte to said ALU circuit on n first input lines, a second input bus for supplying a second n-bit input byte to said ALU circuit on n second input lines, and an output bus for supplying an n-bit output byte from said ALU circuit on n output lines; means for individually defining the operation to be performed by each of said ALU circuits; a plurality of interconnect conductors in the integrated circuit; interconnect means for making programmable connections between the interconnect conductors, said inputs and outputs of said ALU circuits, said digital inputs and outputs of said at least one analog to digital converter, said digital inputs and outputs of said at least one digital to analog converter, and said input/output pads, at least some of said interconnect means comprising user-programmable interconnect elements; said n input lines of the first input bus of at least one of said ALU circuits intersecting n interconnect conductors in first sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form first intersections; first user-programmable interconnect elements disposed at said first intersections; means for programming ones of said first user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between first data on said n interconnect conductors of said first sets of said interconnect conductors and the n input lines of the first input bus of said at least one of said ALU circuits, whereby multiplication and division operations may be performed on said first data by virtue of interconnection.

Claim 8

Tho field programmable, digital signal processing integrated circuit of claim 4, further wherein: said n input lines of the second input bus of at least one of said ALU circuits intersecting n interconnect conductors in second sets of ones of said interconnect conductors connectable to an output bus of another one of said ALU circuits to form second intersections; second user-programmable interconnect elements disposed at said second intersections; means for programming ones of said second user-programmable interconnect elements to cause a bit shift of m places in either of the left and right directions between second data on said n interconnect conductors of said second set of said interconnect conductors and the n input lines of the second input bus of said at least one of said ALU circuits, whereby multiplication and division operations may be performed on said second data by virtue of interconnection.