US5200751A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital to analog converter using a programmable logic array
Assignee: Dallas Semiconductor Corp
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Filing: 1989-06-26
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Granted: 1993-04-06
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Expires: 2009-06-26
Abstract
Abstract A digital to analog converter, wherein a time/voltage array is programmable, to determine which of the possible reference voltages will be enabled by which of the control inputs. Anther set of programmable options, in an output connection matrix, determines which of the internal voltage lines will be connected to which output lines. After the output connection matrix, output selection logic is used to determined which class of output levels are to be used. The output selection logic also preferably includes polarity-reversal gates, so that the polarity of a bipolar output can be reversed.
Inventors
- 👤 Michael D. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:16
CPC Classifications
G; G06; G06J; G06J1/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
119 words
An integrated circuit digital to analog converter, comprising: a voltage source, which provides multiple scaled voltages; a plurality of row lines, connected to receive respective ones of said scaled voltages from said voltage source; each of said row lines including multiple selection transistor locations in series, respective ones of said selection transistors having gates which are connected to control inputs, programmable connections being located to short out selected respective ones of said selection transistors; a plurality of column busses; a plurality of programmable jumpers, each selectably connecting a respective one of said row lines to a respective one of said column busses; said selection transistors being configured so that, multiple ones of said column busses may be driven simultaneously.
Claim 2
Dependent Claim
119 words
An integrated circuit digital to analog converter, comprising: a voltage source, which provides multiple scaled voltages; a plurality of row lines, connected to receive respective ones of said scaled voltages from said voltage source; each of said row lines including multiple selection transistor locations in series, respective ones of said selection transistors having gates which are connected to control inputs, programmable connections being located to short out selected respective ones of said selection transistors; a plurality of column busses; a plurality of programmable jumpers, each selectably connecting a respective one of said row lines to a respective one of said column busses; said selection transistors being configured so that, multiple ones of said column busses may be driven simultaneously.
Claim 3
Dependent Claim
14 words
The integrated circuit of claim 1, comprising at least 64 of said row lines.
Claim 4
Dependent Claim
93 words
The integrated circuit of claim 1, wherein said scaled voltages provided by said voltage source include both voltages which are positive with respect to a reference voltage connection, and also voltages which are negative with respect to a reference voltage connection; and wherein said selection transistors are configured to provide complementary with respect to said reference voltage outputs simultaneously on said column busses; and further comprising polarity reversal logic, connected to receive said outputs of said selection transistors and to selectably exchange said outputs in accordance with the state of a control signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-05 | 1996-10-05 | 1997-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-05 | 2000-10-05 | 2001-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-05 | 2004-10-05 | 2005-04-06 | $7700.00 | Window Closed / Lapsed |