Timing analysis of VLSI circuits

Claim 1

A computer-implemented process for functional timing analysis of a combinational integrated circuit in which there are at least several topologically longest paths comprising the steps of a) first estimating the delay δ of the topologically longest path in a weighted acyclic graph of said circuit, b) transforming said circuit into a functionally equivalent δ path disjoint circuit for the delay value δ, and propagating all the inverters in the circuit to the primary inputs of the circuit, c) performing a multifault test on all primary input fanout points of paths beginning at an input fanout point of length equal to or greater than δ, said multifault test consisting only of all zones or all ones on the said fanouts, and d) if a test is found, treating δ as the delay of the circuit, but if a test is not found, decreasing the values of δ by a unit delay and repeating steps b, c, and d of the process with the decreased values of δ until a test is found.