Rail to rail operational amplifier intermediate stage

Claim 2

An interstage circuit, having positive and negative power supply rails connectable to a source of operating power, and functioning to combine two differential inputs, a first differential input being from an input stage NPN transistor differential amplifier and a second differential input being from an input stage PNP transistor differential amplifier, to produce a single ended output suitable for driving a rail to rail output stage, said interstage circuit comprising: first and second PNP transistors, the emitters of said first and second PNP transistors coupled to receive the first differential input, the base of said first PNP transistor connected to the base of said second PNP transistor, and the collector of said first PNP transistor connected to the base of said first PNP transistor; third and fourth PNP transistors, the emitters of said third and fourth PNP transistors coupled to receive the first differential input, the base of said third PNP transistor connected to the base of said fourth PNP transistor, and the collector of said third PNP transistor connected to the base of said third PNP transistor, the emitter of said third PNP transistor connected to the emitter of said second PNP transistor, and the emitter of said fourth PNP transistor connected to the emitter of said first PNP transistor; first and second NPN transistors, the emitters of said first and second NPN transistors coupled to receive the second differential input, the base of said first NPN transistor connected to the base of said second NPN transistor, and the collector of said first NPN transistor connected to the base of said first NPN transistor; third and fourth NPN transistors, the emitters of said third and fourth NPN transistors coupled to receive the second differential input, the base of said third NPN transistor connected to the base of said fourth NPN transistor, and the collector of said third NPN transistor connected to the base of said third NPN transistor and, further, coupled to receive the collector current of the second PNP transistor, the emitter of said third NPN transistor connected to the emitter of said second NPN transistor, and the emitter of said fourth NPN transistor connected to the emitter of said first NPN transistor; a first resistor that couples the emitters of the first and fourth PNP transistors to the positive power supply rail; a second resistor that couples the emitters of the second and third PNP transistors to the positive power supply rail; a third resistor that couples the emitters of the first and fourth NPN transistors to the negative power supply rail; a fourth resistor that couples the emitters of the second and third NPN transistors to the negative power supply rail; means for coupling the collector of the third PNP transistor to the collector of the second NPN transistor; and means for coupling the collector of the first PNP transistor to a first substantially constant current source having a first current; means for coupling the collector of the first NPN transistor to a second substantially constant current source having a second current, said second current being substantially equal to said first current; and means for coupling the collector of the fourth PNP transistor to the collector of the fourth NPN transistor, wherein the single ended output appears at an output node between the collector of the fourth PNP transistor and the collector of the fourth NPN transistor.

Claim 3

The interstage circuit of claim 1, wherein said second current source is said first current source.

Claim 4

The interstage circuit of claim 1, wherein said first resistor is matched to said second resistor.

Claim 5

The interstage circuit of claim 1, wherein said third resistor is matched to said fourth resistor.

Claim 6

The interstage circuit of claim 1, wherein said first resistor is matched to said second resistor, and said third resistor is matched to said fourth resistor.

Claim 7

The interstage circuit of claim 1 further comprising: a first frequency compensation capacitor connected between the base of said first PNP transistor and the base of said third PNP transistor; and a second frequency compensation capacitor connected between the base of said first NPN transistor and the base of said third NPN transistor whereby the gain of said interstage circuit is lowered for high frequency inputs.

Claim 8

An combined interstage and output stage circuit, the interstage circuit having positive and negative power supply rails connectable to a source of operating power, and functioning to combine two differential inputs, a first differential input being from an input stage NPN transistor differential amplifier and a second differential input being from an input stage PNP transistor differential amplifier, to produce a single ended output suitable for driving a rail to rail output stage, said interstage circuit comprising: first and second PNP transistors, the emitters of said first and second PNP transistors coupled to receive the first differential input, the base of said first PNP transistor connected to the base of said second PNP transistor, and the collector of said first PNP transistor connected to the base of said first PNP transistor; third and fourth PNP transistors, the emitters of said third and fourth PNP transistors coupled to receive the first differential input, the base of said third PNP transistor connected to the base of said fourth PNP transistor, and the collector of said third PNP transistor connected to the base of said third PNP transistor, the emitter of said third PNP transistor connected to the emitter of said second PNP transistor, and the emitter of said fourth PNP transistor connected to the emitter of said first PNP transistor; first and second NPN transistors, the emitters of said first and second NPN transistors coupled to receive the second differential input, the base of said first NPN transistor connected to the base of said second NPN transistor, and the collector of said first NPN transistor connected to the base of said first NPN transistor; third and fourth NPN transistors, the emitters of said third and fourth NPN transistors coupled to receive the second differential input, the base of said third NPN transistor connected to the base of said fourth NPN transistor, and the collector of said third NPN transistor connected to the base of said third NPN transistor and, further, coupled to receive the collector current of the second PNP transistor, the emitter of said third NPN transistor connected to the emitter of said second NPN transistor, and the emitter of said fourth NPN transistor connected to the emitter of said first NPN transistor; a first resistor that couples the emitters of the first and fourth PNP transistors to the positive power supply rail; a second resistor that couples the emitters of the second and third PNP transistors to the positive power supply rail; a third resistor that couples the emitters of the first and fourth NPN transistors to the negative power supply rail; a fourth resistor that couples the emitters of the second and third NPN transistors to the negative power supply rail; means for coupling the collector of the third PNP transistor to the collector of the second NPN transistor; and means for coupling the collector of the first PNP transistor to a first substantially constant current source having a first current; means for coupling the collector of the first NPN transistor to a second substantially constant current source having a second current, said second current being substantially equal to said first current; and means for coupling the collector of the fourth PNP transistor to the collector of the fourth NPN transistor, wherein the single ended output appears at an output node between the collector of the fourth PNP transistor and the collector of the fourth NPN transistor; and the output stage having output stage input and output terminals, positive and negative power supply rails connectable to a source of operating power and a pair of complementary common-emitter output transistors coupled between said power supply rails without any intervening circuit components, whereby the collectors of said output transistors comprise said output stage output terminal, said output stage comprising: a pair of complementary emitter follower buffer drivers coupled to drive the bases of said output transistors; a complementary pair of differential amplifiers, having inverting and non-inverting inputs and having outputs coupled to drive said buffer drivers; a PNP voltage buffer transistor the emitter of which is coupled to the inverting inputs of said pair of differential amplifiers, the base of which is coupled to a first source of bias potential, and the collector of which is coupled to the base of said second NPN transistor; means for coupling the non-inverting inputs of said pair of differential amplifiers together to comprise an input node; means for coupling the input node to said output stage input terminal; and means for coupling said output stage input terminal to said interstage circuit output terminal.

Claim 9

An combined interstage and output stage circuit, the interstage circuit having positive and negative power supply rails connectable to a source of operating power, and functioning to combine two differential inputs, a first differential input being from an input stage NPN transistor differential amplifier and a second differential input being from an input stage PNP transistor differential amplifier, to produce a single ended output suitable for driving a rail to rail output stage, said interstage circuit comprising: first and second PNP transistors, the emitters of said first and second PNP transistors coupled to receive the first differential input, the base of said first PNP transistor connected to the base of said second PNP transistor, and the collector of said first PNP transistor connected to the base of said first PNP transistor; third and fourth PNP transistors, the emitters of said third and fourth PNP transistors coupled to receive the first differential input, the base of said third PNP transistor connected to the base of said fourth PNP transistor, and the collector of said third PNP transistor connected to the base of said third PNP transistor, the emitter of said third PNP transistor connected to the emitter of said second PNP transistor, and the emitter of said fourth PNP transistor connected to the emitter of said first PNP transistor; first and second NPN transistors, the emitters of said first and second NPN transistors coupled to receive the second differential input, the base of said first NPN transistor connected to the base of said second NPN transistor, and the collector of said first NPN transistor connected to the base of said first NPN transistor; third and fourth NPN transistors, the emitters of said third and fourth NPN transistors coupled to receive the second differential input, the base of said third NPN transistor connected to the base of said fourth NPN transistor, and the collector of said third NPN transistor connected to the base of said third NPN transistor and, further, coupled to receive the collector current of the second PNP transistor, the emitter of said third NPN transistor connected to the emitter of said second NPN transistor, and the emitter of said fourth NPN transistor connected to the emitter of said first NPN transistor; a first resistor that couples the emitters of the first and fourth PNP transistors to the positive power supply rail; a second resistor that couples the emitters of the second and third PNP transistors to the positive power supply rail; a third resistor that couples the emitters of the first and fourth NPN transistors to the negative power supply rail; a fourth resistor that couples the emitters of the second and third NPN transistors to the negative power supply rail; means for coupling the collector of the third PNP transistor to the collector of the second NPN transistor; and means for coupling the collector of the first PNP transistor to a first substantially constant current source having a first current; means for coupling the collector of the first NPN transistor to a second substantially constant current source having a second current, said second current being substantially equal to said first current; and means for coupling the collector of the fourth PNP transistor to the collector of the fourth NPN transistor, wherein the single ended output appears at an output node between the collector of the fourth PNP transistor and the collector of the fourth NPN transistor; and the output stage having output stage input and output terminals, positive and negative power supply rails connectable to a source of operating power and a pair of complementary common-emitter output transistors coupled between said power supply rails without any intervening circuit components, whereby the collectors of said output transistors comprise said output stage output terminal, said output stage comprising: a pair of complementary emitter follower buffer drivers coupled to drive the bases of said output transistors; a complementary pair of differential amplifiers, having inverting and non-inverting inputs and having outputs coupled to drive said buffer drivers; a PNP voltage buffer transistor the emitter of which is coupled to the inverting inputs of said pair of differential amplifiers, the base of which is coupled to a first source of bias potential, and the collector of which is coupled to the base of said second NPN transistor; means for coupling the non-inverting inputs of said pair of differential amplifiers together to comprise an input node; means for coupling the input node to said output stage input terminal; and means for coupling said output stage input terminal to said interstage circuit output terminal.

Claim 10

The combined interstage and output stage circuit of claim 7, further comprising: a NPN buffer voltage transistor, the emitter of which is coupled to the emitter of the PNP buffer voltage transistor, the base of which is connected to a second source of bias potential, and the collector of which is coupled to the base of the first PNP transistor.

Claim 11

The combined interstage and output stage circuit of claim 7, wherein said first source of bias potential is half the power supply rail.

Claim 12

The combined interstage and output stage circuit of claim 8, wherein said second source of bias potential is half the power supply rail, plus an amount of voltage developed across one diode.

Claim 13

A interstage circuit functioning to combine a first differential voltage and a second differential voltage, the first and second differential voltages being either positive or negative, to produce a current at a single ended output, said interstage circuit comprising: first means for generating a first current, the first current exceeding a first bias current by an amount corresponding to the first differential voltage, if the first differential voltage is positive, and the first current being equal to the first bias current if the first differential voltage is not positive; second means for generating a second current, the second current exceeding a second bias current by an amount corresponding to the second differential voltage, if the second differential voltage is positive, and the second current being equal to the second bias current if the second differential voltage is not positive; third means for generating a third current, the third current exceeding said second current by an amount corresponding to the first differential voltage, if the first differential voltage is negative, and the third current being equal to said second bias current if the first differential voltage is not negative; and fourth means for generating a fourth current, the fourth current exceeding said first current by an amount corresponding to the second differential voltage, if the second differential voltage is negative, and the fourth current being equal to said first current if the second differential voltage is not negative; and fifth means, for subtracting said third current from said fourth current to produce the current at the single ended output.

Claim 14

A interstage circuit functioning to combine a first differential voltage and a second differential voltage, the first and second differential voltages being either positive or negative, to produce a current at a single ended output, said interstage circuit comprising: first means for generating a first current, the first current exceeding a first bias current by an amount corresponding to the first differential voltage, if the first differential voltage is positive, and the first current being equal to the first bias current if the first differential voltage is not positive; second means for generating a second current, the second current exceeding a second bias current by an amount corresponding to the second differential voltage, if the second differential voltage is positive, and the second current being equal to the second bias current if the second differential voltage is not positive; third means for generating a third current, the third current exceeding said second current by an amount corresponding to the first differential voltage, if the first differential voltage is negative, and the third current being equal to said second bias current if the first differential voltage is not negative; and fourth means for generating a fourth current, the fourth current exceeding said first current by an amount corresponding to the second differential voltage, if the second differential voltage is negative, and the fourth current being equal to said first current if the second differential voltage is not negative; and fifth means, for subtracting said third current from said fourth current to produce the current at the single ended output.

Claim 15

The interstage circuit of claim 11, further comprising: a first bias current generator for producing said first bias current, said first bias current being substantially constant; and a second bias current generator for producing said second bias current, said second bias current being substantially constant.

Claim 16

The interstage circuit of claim 12, wherein said first bias current generator is said second bias current generator.

Claim 17

The interstage circuit of claim 11, further comprising: means for generating said first differential voltage based on a first differential current; and means for generating said second differential voltage based on a second differential current.