Patent US5455438A successfully refreshed from Google Patents.
US5455438A
Expired / Lapsed
US
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Semiconductor integrated circuit device in which kink current disturbances of MOS transistors are suppressed
Assignee: Renesas Electronics Corp
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Filing: 1993-06-01
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Granted: 1995-10-03
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Expires: 2013-06-01
Abstract
Abstract Disclosed is a semiconductor integrated circuit device having a plurality of fine memory devices and its fabrication method, and particularly to a semiconductor integrated circuit device capable of suppressing the kink current disturbance of MOS transistors without reducing the junction characteristic of the diffusion layers and its fabrication method. In this device, an angle between the lower surface of each edge of a field oxide formed in an environmental device area, i.e. a peripheral circuit area, and the main surface of a semiconductor substrate is smaller than an angle between the lower surface of each edge of a field oxide formed in a memory cell area and the main surface of the semiconductor substrate. Further, the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the environmental device area is larger than the extension, in the direction of being parallel to the main surface of the semiconductor substrate, of each edge of the field oxide in the memory cell area.
Inventors
- 👤 Naotaka Hashimoto
- 👤 Toshiaki Yamanaka
- 👤 Takashi Hashimoto
- 👤 Akihiro Shimizu
- 👤 Nagatoshi Ohki
- 👤 Hiroshi Ishida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:39
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0125; H10W10/0126; H10W10/10; H10W10/17; H10B; H10B12/00; H10B12/30; H10W10/014; H10W10/0148; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
258 words
A semiconductor integrated circuit device comprising: a memory cell area including a plurality of memory elements formed on a main surface region of a semiconductor substrate; a peripheral area including a plurality of peripheral elements formed on the main surface region of said semiconductor substrate; and field isolation insulating films including a first field isolation insulating film for isolating said memory elements from said peripheral elements which are disposed adjacent thereto being formed between said memory cell area and said peripheral area, a second field isolation insulating film for isolating said memory elements from each other being formed on said memory cell area and a third field isolation insulating film for isolating said peripheral elements from each other being formed on said peripheral area, wherein an angle between a substantially linear part of a lower surface of each edge portion of said third field isolation insulating film and the main surface of said semiconductor substrate is smaller than an angle between a substantially linear part of the lower surface of each edge portion of said second field isolation insulating film and the main surface of said semiconductor substrate, and wherein an impurity concentration on the surface region of said semiconductor substrate interposed between a source region and a drain region of individual MOS transistor elements, which are disposed in said memory cell area, is higher than the impurity concentration on the surface region of said semiconductor substrate interposed between said source region and said drain region of individual MOS transistor elements which are disposed in said peripheral area.
Claim 2
Dependent Claim
258 words
A semiconductor integrated circuit device comprising: a memory cell area including a plurality of memory elements formed on a main surface region of a semiconductor substrate; a peripheral area including a plurality of peripheral elements formed on the main surface region of said semiconductor substrate; and field isolation insulating films including a first field isolation insulating film for isolating said memory elements from said peripheral elements which are disposed adjacent thereto being formed between said memory cell area and said peripheral area, a second field isolation insulating film for isolating said memory elements from each other being formed on said memory cell area and a third field isolation insulating film for isolating said peripheral elements from each other being formed on said peripheral area, wherein an angle between a substantially linear part of a lower surface of each edge portion of said third field isolation insulating film and the main surface of said semiconductor substrate is smaller than an angle between a substantially linear part of the lower surface of each edge portion of said second field isolation insulating film and the main surface of said semiconductor substrate, and wherein an impurity concentration on the surface region of said semiconductor substrate interposed between a source region and a drain region of individual MOS transistor elements, which are disposed in said memory cell area, is higher than the impurity concentration on the surface region of said semiconductor substrate interposed between said source region and said drain region of individual MOS transistor elements which are disposed in said peripheral area.
Claim 3
Dependent Claim
44 words
A semiconductor integrated circuit device according to claim 1, wherein said angle between the substantially linear part of the lower surface of each edge portion of said third field isolation insulating film and the main surface of said semiconductor substrate is 60° or less.
Claim 4
Dependent Claim
47 words
A semiconductor integrated circuit device according to claim 1, wherein a thickness of a gate insulating film for said MOS transistor elements, disposed in said memory cell area, is larger than that of the gate insulating film for said MOS transistor elements formed in said peripheral area.
Claim 5
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 1, wherein said plurality of memory elements and said plurality of peripheral elements are comprised of MOS transistors, respectively.
Claim 6
Dependent Claim
47 words
A semiconductor integrated circuit device according to claim 2, wherein a thickness of a gate insulating film for said MOS transistor elements disposed in said memory cell area is larger than that of the gate insulating film for said MOS transistor elements formed in said peripheral area.
Claim 7
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 5, wherein said plurality of memory elements and said plurality of peripheral elements are comprised of MOS transistors, respectively.
Claim 8
Dependent Claim
27 words
A semiconductor integrated circuit device according to claim 3, wherein said plurality of memory elements and said plurality of peripheral elements are comprised of MOS transistors, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |