Patent US5455435A successfully refreshed from Google Patents.
US5455435A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Late programming mask ROM and process for producing the same
Assignee: United Microelectronics Corp
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Filing: 1993-11-09
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Granted: 1995-10-03
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Expires: 2013-11-09
Abstract
Abstract A late programming mask ROM integrated circuit and a process for producing the same. The mask ROM integrated circuit has a silicon substrate, and a plurality of memory cells formed on the silicon substrate. Each memory cell consists of a transistor element and a diode element electrically connected in series. Each transistor element has a drain layer, a channel layer, a source layer all stacked on the silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on the silicon substrate. The gate electrode regions and the upright drain/channel/source structure regions of the transistor elements are alternately arranged in an adjacent fashion along a substantially horizontal direction. Each diode element is formed by one upright drain/channel/source structure and a diode layer formed on or under the upright drain/channel/source structure.
Inventors
- 👤 Chien-Chih Fu
- 👤 Fong-Chun Lee
- 👤 Nan-Chueh Wang
- 👤 Shiao-Fen Pao
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 11:32
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/27; H10B20/40
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
127 words
A ROM integrated circuit comprising: a silicon substrate; and a plurality of memory cells formed on said silicon substrate, each memory cell including a transistor element and a diode element electrically connected in series, each transistor element having a drain layer, a channel layer, a source layer all stacked on said silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on said silicon substrate; said gate electrode regions and said upright drain/channel/source structure regions of said transistor elements being alternately arranged in an adjacent fashion along a substantially horizontal direction, and each upright drain/channel/source structure region providing, at two opposite sides, drain/channel/source structures for two transistor elements, which are respectively controlled by two adjacent gate electrodes.
Claim 2
Dependent Claim
127 words
A ROM integrated circuit comprising: a silicon substrate; and a plurality of memory cells formed on said silicon substrate, each memory cell including a transistor element and a diode element electrically connected in series, each transistor element having a drain layer, a channel layer, a source layer all stacked on said silicon substrate in a substantially vertical direction to form an upright drain/channel/source structure region, and a gate electrode region formed on said silicon substrate; said gate electrode regions and said upright drain/channel/source structure regions of said transistor elements being alternately arranged in an adjacent fashion along a substantially horizontal direction, and each upright drain/channel/source structure region providing, at two opposite sides, drain/channel/source structures for two transistor elements, which are respectively controlled by two adjacent gate electrodes.
Claim 3
Dependent Claim
41 words
The ROM integrated circuit as claimed in claim 1, further comprising a plurality of diode layers formed in said silicon substrate and under said upright drain/channel/source structure regions, said diode elements being formed in combination with said upright drain/channel/source structure regions.
Claim 4
Dependent Claim
29 words
The ROM integrated circuit as claimed in claim 2, wherein said mask ROM integrated circuit is programmable by implanting a dopant into the channel layers of designated memory cells.
Claim 5
Dependent Claim
36 words
The mask ROM integrated circuit as claimed in claim 3, further comprising a passivation layer formed over said gate electrode regions and said drain/channel/source structure regions, with a plurality of pad openings formed in designated regions.
Claim 6
Dependent Claim
34 words
The mask ROM integrated circuit as claimed in claim 2, wherein said mask ROM integrated circuit is programmable by etching to remove at least part of the gate electrode regions of designated memory cells.
Claim 7
Dependent Claim
38 words
The mask ROM integrated circuit as claimed in claim 1, further comprising a plurality of diode layers formed on said upright drain/channel/source structure regions, and said diode elements being formed in combination with said upright drain/channel/source structure regions.
Claim 8
Dependent Claim
30 words
The mask ROM integrated circuit as claimed in claim 6, wherein said mask ROM integrated circuit is programmable by implanting a dopant into the channel layers of designated memory cells.
Claim 9
Dependent Claim
35 words
The mask ROM integrated circuit as claimed in claim 7, further comprising a passivation layer formed over said diode layers and said gate electrode regions, with a plurality of pad openings formed in designated regions.
Claim 10
Dependent Claim
34 words
The mask ROM integrated circuit as claimed in claim 6, wherein said mask ROM integrated circuit is programmable by etching to remove at least part of the gate electrode regions of designated memory cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-10-02 | 1999-04-03 | 1999-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-10-02 | 2003-04-03 | 2003-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-10-02 | 2007-04-03 | 2007-10-03 | $7700.00 | Window Closed / Lapsed |