Method of fabricating an ASIC cell having multiple contacts

Claim 1

A method of fabricating an application specific integrated circuit containing an array of devices, the method permitting alteration of a single conducting layer to customize the integrated circuit and further permitting traversing connections, the method comprising: (a) fabricating a replicated pattern of devices upon a substrate, each device defining a cell area and including a first region, a second region, and a third region, adjacent device cells abutting one another; (b) depositing over each device cell area a first layer of conducting material defining first, second and third stripes; each said first stripe being sized to create at least two contact region thereon for redundant upward electrical contact, and making redundant downward electrical contact with said first region; each said second stripe being sized to create at least two contact regions thereon for redundant upward electrical contact, and making redundant downward electrical contact with said second region; each said third stripe being sized to create at least two contact regions thereon for redundant upward electrical contact, and making redundant downward electrical contact with said third region; (c) depositing, over said first layer of conducting material, a layer of insulating material defining an option opening disposed over each said contact region on each said stripe for facilitating upward electrical contact with each said stripe, a matrix of option openings being formed thereby; each said option opening capable of being opened or remaining closed during fabrication of the integrated circuit; an opened option opening facilitating upward electrical contact with an underlying said contact region of a said stripe and thus with a region of said device; each said stripe thereby providing a redundancy of connections between a region of said device and a portion of said matrix of option openings; a closed option opening insulating an underlying said region of a said stripe and thus a region of said device from any layer overlying said layer of insulating material; (d) depositing, over said layer of insulating material, a second layer of conductive material forming traces customizing the integrated circuit; a first said trace being in downward electrical contact with a region of said device if a said option opening underlying said trace is opened during fabrication; a second said trace being allowed to traverse a region of said cell area by leaving unopened any said option opening beneath said traversing trace; said redundancy of connections between said device and said matrix of option openings permitting a said second trace to traverse a region of said cell area while still providing at least one electrical contact to each region of said device for use by said first trace; the redundancy of connections and ability to traverse permitting customization of the integrated circuit by altering said second layer of conductive materials and by selectively opening option openings in said layer of insulating material, and further permitting said device cell areas to abut without requiring dedicated space to accommodate traversing traces.

Claim 2

A method of fabricating an application specific integrated circuit containing an array of devices, the method permitting alteration of a single conducting layer to customize the integrated circuit and further permitting traversing connections, the method comprising: (a) fabricating a replicated pattern of devices upon a substrate, each device defining a cell area and including a first region, a second region, and a third region, adjacent device cells abutting one another; (b) depositing over each device cell area a first layer of conducting material defining first, second and third stripes; each said first stripe being sized to create at least two contact region thereon for redundant upward electrical contact, and making redundant downward electrical contact with said first region; each said second stripe being sized to create at least two contact regions thereon for redundant upward electrical contact, and making redundant downward electrical contact with said second region; each said third stripe being sized to create at least two contact regions thereon for redundant upward electrical contact, and making redundant downward electrical contact with said third region; (c) depositing, over said first layer of conducting material, a layer of insulating material defining an option opening disposed over each said contact region on each said stripe for facilitating upward electrical contact with each said stripe, a matrix of option openings being formed thereby; each said option opening capable of being opened or remaining closed during fabrication of the integrated circuit; an opened option opening facilitating upward electrical contact with an underlying said contact region of a said stripe and thus with a region of said device; each said stripe thereby providing a redundancy of connections between a region of said device and a portion of said matrix of option openings; a closed option opening insulating an underlying said region of a said stripe and thus a region of said device from any layer overlying said layer of insulating material; (d) depositing, over said layer of insulating material, a second layer of conductive material forming traces customizing the integrated circuit; a first said trace being in downward electrical contact with a region of said device if a said option opening underlying said trace is opened during fabrication; a second said trace being allowed to traverse a region of said cell area by leaving unopened any said option opening beneath said traversing trace; said redundancy of connections between said device and said matrix of option openings permitting a said second trace to traverse a region of said cell area while still providing at least one electrical contact to each region of said device for use by said first trace; the redundancy of connections and ability to traverse permitting customization of the integrated circuit by altering said second layer of conductive materials and by selectively opening option openings in said layer of insulating material, and further permitting said device cell areas to abut without requiring dedicated space to accommodate traversing traces.

Claim 13

A method of fabricating an application specific integrated circuit containing an array of devices, the method permitting alteration of a single conducting layer to customize the integrated circuit and permitting traversing connections, the method comprising: (a) fabricating a pattern of replicated devices upon a substrate, each device defining a cell area and including an first region, at least one second region, and at least one third region, adjacent device cells abutting one another; (b) depositing over said pattern of devices a first layer of insulating material that defines a through opening overlying each said first, second and third region; (c) depositing over said first layer of insulating material a first layer of conducting material including a pattern of third traces and first traces, a third and first pair of said traces overlying each said cell area; a portion of said third trace overlying and making redundant downward electrical contact, through a said opening in said first layer of insulating material, with said third region of said device; a portion of said first trace overlying and making redundant downward electrical contact, through a said opening in said first layer of insulating material, with said first region of said device; each said third and first trace being sized to permit redundant upward electrical contact at at least two regions thereon; (d) depositing over said first layer of conducting material a second layer of insulating material defining at least first, second and third through openings over said cell area; said first opening permitting downward electrical contact therethrough with said third on said first layer of conducting material; said second opening permitting downward electrical contact therethrough with said first trace on said first layer of conducting material; said third opening permitting downward electrical contact therethrough with said second region; (e) depositing over said second layer of insulating material a second layer of conducting material defining a pattern of third, second and first stripes; said third stripe being sized to create at least two redundant contact regions thereon and making downward electrical contact, through an opening in said second insulating layer, with said third trace on said first layer of conducting material; said second stripe being sized to create at least two redundant contact regions thereon and making downward electrical contact through an opening in said second insulating layer and in said first insulating layer with said second region; said first stripe being sized to create at least two redundant contact regions thereon and making downward electrical contact, through an opening in said second insulating layer, with said first trace on said first layer of conducting material; said third, second and first stripes thus each presenting at least two contact regions thereon for making electrical contact, respectively, with said third, second and first regions of said device; (f) depositing over said second layer of conducting material a third layer of insulating material defining an option opening disposed over each said contact region for upward electrical contact on each said stripe, a matrix of option openings being formed thereby, each said stripe providing a redundancy of connections between a region of said device and a portion of said matrix of option openings; each said option opening capable of being opened or remaining closed during fabrication of the integrated circuit; each opened option opening facilitating upward electrical contact with an underlying said contact region of a said stripe and thus with a region of said device; each closed option opening insulating an underlying said contact region of a said Stripe and thus insulating a region of said device from any layer overlying said layer of insulating material; (g) depositing over said third layer of insulating material a third layer of conductive material forming traces customizing the integrated circuit; a first said trace being in downward electrical contact with a region of said device if a said option opening underlying said trace was opened during fabrication; a second said trace being allowed to traverse a region of said cell area by not opening any said option opening beneath said traversing trace; said redundancy of connections between said device and said matrix of option openings permitting said second trace to traverse a region of said cell area while still providing at least one electrical contact to each region of said device for use by said first trace; the redundancy of connections and ability to traverse permitting customization of the integrated circuit by altering said third layer of conductive materials and by selectively opening option openings in said third layer of insulating material, and permitting said device cell areas to abut without requiring dedicated space to accommodate traversing traces.

Claim 14

A method of fabricating an application specific integrated circuit containing an array of devices, the method permitting alteration of a single conducting layer to customize the integrated circuit and permitting traversing connections, the method comprising: (a) fabricating a pattern of replicated devices upon a substrate, each device defining a cell area and including an first region, at least one second region, and at least one third region, adjacent device cells abutting one another; (b) depositing over said pattern of devices a first layer of insulating material that defines a through opening overlying each said first, second and third region; (c) depositing over said first layer of insulating material a first layer of conducting material including a pattern of third traces and first traces, a third and first pair of said traces overlying each said cell area; a portion of said third trace overlying and making redundant downward electrical contact, through a said opening in said first layer of insulating material, with said third region of said device; a portion of said first trace overlying and making redundant downward electrical contact, through a said opening in said first layer of insulating material, with said first region of said device; each said third and first trace being sized to permit redundant upward electrical contact at at least two regions thereon; (d) depositing over said first layer of conducting material a second layer of insulating material defining at least first, second and third through openings over said cell area; said first opening permitting downward electrical contact therethrough with said third on said first layer of conducting material; said second opening permitting downward electrical contact therethrough with said first trace on said first layer of conducting material; said third opening permitting downward electrical contact therethrough with said second region; (e) depositing over said second layer of insulating material a second layer of conducting material defining a pattern of third, second and first stripes; said third stripe being sized to create at least two redundant contact regions thereon and making downward electrical contact, through an opening in said second insulating layer, with said third trace on said first layer of conducting material; said second stripe being sized to create at least two redundant contact regions thereon and making downward electrical contact through an opening in said second insulating layer and in said first insulating layer with said second region; said first stripe being sized to create at least two redundant contact regions thereon and making downward electrical contact, through an opening in said second insulating layer, with said first trace on said first layer of conducting material; said third, second and first stripes thus each presenting at least two contact regions thereon for making electrical contact, respectively, with said third, second and first regions of said device; (f) depositing over said second layer of conducting material a third layer of insulating material defining an option opening disposed over each said contact region for upward electrical contact on each said stripe, a matrix of option openings being formed thereby, each said stripe providing a redundancy of connections between a region of said device and a portion of said matrix of option openings; each said option opening capable of being opened or remaining closed during fabrication of the integrated circuit; each opened option opening facilitating upward electrical contact with an underlying said contact region of a said stripe and thus with a region of said device; each closed option opening insulating an underlying said contact region of a said Stripe and thus insulating a region of said device from any layer overlying said layer of insulating material; (g) depositing over said third layer of insulating material a third layer of conductive material forming traces customizing the integrated circuit; a first said trace being in downward electrical contact with a region of said device if a said option opening underlying said trace was opened during fabrication; a second said trace being allowed to traverse a region of said cell area by not opening any said option opening beneath said traversing trace; said redundancy of connections between said device and said matrix of option openings permitting said second trace to traverse a region of said cell area while still providing at least one electrical contact to each region of said device for use by said first trace; the redundancy of connections and ability to traverse permitting customization of the integrated circuit by altering said third layer of conductive materials and by selectively opening option openings in said third layer of insulating material, and permitting said device cell areas to abut without requiring dedicated space to accommodate traversing traces.