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US5453157A Expired / Lapsed US ⏱️ 0.0 years remaining

Low temperature anisotropic ashing of resist for semiconductor fabrication

Assignee: Texas Instruments Inc
•
Filing: 1994-05-16
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Granted: 1995-09-26
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Expires: 2014-05-16
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Abstract

Abstract This invention encompasses using anisotropic plasma at a low temperature to strip resist from a semiconductor wafer. A semiconductor wafer 10 is placed in a reactor 26 which contains an oxygen plasma source 28. The oxygen plasma source 28 emits oxygen plasma 32 which is drawn towards the biased wafer 10, exposing the resist layer 22 of the wafer to anisotropic oxygen plasma. A sensor 30 detects when the ashing of the resist is complete, and then the plasma source is turned off. Advantages of the invention include the ability to remove resist from wafers without damaging polymeric dielectric layers, which are sensitive to the harsh effects of traditional resist removal methods. With the present invention, very little damage occurs to the material on the sidewalls of vias.

Inventors

  • 👤 Shin-puu Jeng

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 00:41
CPC Classifications
H; H10; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/286; H10P50/287; G; G03; G03F; G03F7/00; G03F7/26; G03F7/42; G03F7/427; H10P76/00; H10P76/20; H10P76/204; H10P76/2041

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 63 words
A method for removing resist from a semiconductor wafer having a substrate, including the steps of: depositing a metal layer over said substrate; coating said substrate with a polymeric layer; applying an inorganic layer over said polymeric layer; applying a resist layer over said inorganic layer; patterning said resist layer; etching said inorganic layer; and ashing said resist with an anisotropic oxygen plasma.
Claim 2
Independent Claim 63 words
A method for removing resist from a semiconductor wafer having a substrate, including the steps of: depositing a metal layer over said substrate; coating said substrate with a polymeric layer; applying an inorganic layer over said polymeric layer; applying a resist layer over said inorganic layer; patterning said resist layer; etching said inorganic layer; and ashing said resist with an anisotropic oxygen plasma.
Claim 3
Independent Claim 58 words
A system for removing resist from a semiconductor wafer, comprising: a reactor; a wafer having a polymeric layer positioned within said reactor; an oxygen plasma source located inside said reactor; a wafer biasing apparatus to anisotropically direct ions from a plasma toward said wafer; and a sensor located inside said reactor to detect when resist has been removed.
Claim 4
Independent Claim 58 words
A system for removing resist from a semiconductor wafer, comprising: a reactor; a wafer having a polymeric layer positioned within said reactor; an oxygen plasma source located inside said reactor; a wafer biasing apparatus to anisotropically direct ions from a plasma toward said wafer; and a sensor located inside said reactor to detect when resist has been removed.
Claim 5
Dependent Claim 19 words
The system of claim 2 wherein said system is shut off when said sensor detects completion of resist removal.
Claim 6
Independent Claim 52 words
A system for removing resist from a semiconductor wafer, comprising: a reactor; a wafer having a polymeric layer positioned Within said reactor; an oxygen plasma source located inside said reactor; and a wafer biasing apparatus to anisotropically direct ions from a plasma toward said wafer, wherein said wafer is biased to ground.
Claim 7
Independent Claim 52 words
A system for removing resist from a semiconductor wafer, comprising: a reactor; a wafer having a polymeric layer positioned Within said reactor; an oxygen plasma source located inside said reactor; and a wafer biasing apparatus to anisotropically direct ions from a plasma toward said wafer, wherein said wafer is biased to ground.

References Cited (Backward Citations)

JPS59222929A Cited
US4464460A Cited
JPS60262151A Cited
JPS63160227A Cited
EP0394739A2 Cited
US5312717A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-09-25 1999-03-27 1999-09-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-09-25 2003-03-27 2003-09-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-09-25 2007-03-27 2007-09-26 $7700.00 Window Closed / Lapsed

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