Multi-processor system with fault detection

Claim 2

A multi-processor system with fault detection, comprising: a monitor circuit including a register with a flag; a first processor module including a processor and means for setting the flag at predetermined time intervals; and a second processor module including a processor and means for resetting the flag at predetermined time intervals which are offset from said time intervals of said first processor module; wherein the monitor circuit further includes means for detecting a non-reset condition of the flag indicative of a fault in the second processor module.

Claim 3

A multi-processor system with fault detection, comprising: a first processor module including a register with a flag and means for setting the flag at predetermined time intervals; a second processor module including means for resetting the flag; and a monitor circuit for reading a status of the flag at predetermined time intervals offset from said predetermined time intervals of said first processor module and for detecting a non-set status of the flag indicative of a fault in the first processor module.

Claim 4

A multi-processor system with fault detection, comprising: a first processor module including a register with a flag and means for setting the flag at predetermined time intervals; a second processor module including means for resetting the flag; and a monitor circuit for reading a status of the flag at predetermined time intervals offset from said predetermined time intervals of said first processor module and for detecting a non-set status of the flag indicative of a fault in the first processor module.

Claim 5

A multi-processor system with fault detection, comprising: a data bus; a first processor module, connected to the data bus; a second processor module, connected to the data bus; wherein the first processor module further includes a first monitor circuit including a register with a flag, the first monitor circuit further including means for setting the flag after a predetermined period; wherein the second processor module further includes a second monitor circuit including means for outputting a signal to the first processor module via the data bus to reset the flag; and wherein the first monitor circuit further includes means for detecting a non-reset status of the flag indicative of a fault in the second processor.

Claim 6

A multi-processor system with fault detection, comprising: a data bus; a first processor module, connected to the data bus; a second processor module, connected to the data bus; wherein the first processor module further includes a first monitor circuit including a register with a flag, the first monitor circuit further including means for setting the flag after a predetermined period; wherein the second processor module further includes a second monitor circuit including means for outputting a signal to the first processor module via the data bus to reset the flag; and wherein the first monitor circuit further includes means for detecting a non-reset status of the flag indicative of a fault in the second processor.

Claim 7

A multi-processor system with fault detection, comprising: a data bus; a first processor module, connected to the data bus; a second processor module, connected to the data bus; wherein the first processor module further includes a register with a flag, means for setting the flag after a first predetermined period, and means for outputting a flag signal containing the status of the flag to the data bus; and wherein the second processor module further includes a monitor circuit including means for accepting the flag signal from the data bus and for reading the status of the flag after a second predetermined period longer than the first predetermined period, and for detecting a non-set status of the flag indicative of a fault in the first processor module.

Claim 8

A multi-processor system with fault detection, comprising: a data bus; a first processor module, connected to the data bus; a second processor module, connected to the data bus; wherein the first processor module further includes a register with a flag, means for setting the flag after a first predetermined period, and means for outputting a flag signal containing the status of the flag to the data bus; and wherein the second processor module further includes a monitor circuit including means for accepting the flag signal from the data bus and for reading the status of the flag after a second predetermined period longer than the first predetermined period, and for detecting a non-set status of the flag indicative of a fault in the first processor module.

Claim 11

A method for detecting a fault according to claim 5, further including the step of: comparing an output of the first processor of each processor module with an output of the respective second processor of each processor module to detect a fault.

Claim 12

A method for detecting a fault according to claim 6, further including the steps of: associating a fault with the second processor module when the flag of the first processor module is detected in the first condition; and associating a fault with the first processor module when the flag of the first processor module is detected in the second condition.

Claim 13

A method for detecting a fault according to claim 5, further including the steps of: associating a fault with the second processor module when the flag of the first processor module is detected in the first condition; and associating a fault with the first processor module when the flag of the first processor module is detected in the second condition.

Claim 16

A method for detecting a fault according to claim 9, further including the steps of: associating a fault with the second processor module when the flag of the first processor module is detected in the first condition; and associating a fault with the first processor module when the flag of the first processor module is detected in the second condition.

Claim 17

A processor module for a multi-processor system with fault detection, the multi-processor system including a plurality of processor modules connected to a data bus, said processor module comprising: a starting circuit generating a first start signal and generating a second start signal delayed from said first start signal; a memory for storing data connected to a first data path; a bus interface connected to the data bus for transferring data between said data bus and said memory; a first processor connected to said first data path, having an input means for accepting said first start signal, for processing data stored in said memory, and for outputting a first output on said first data path; a second processor connected to a second data path having input means for accepting said second start signal so that operation of said second processor is delayed and overlapping in time with respect to the first processor, said second processor outputting a second output on said second data path which is delayed with respect to the first output; a comparator having means connected to said first data path for receiving the first output from the first processor, and means connected to said second data path for receiving the second output from the second processor, said comparator comparing said first output and said second output and outputting an error signal on a third data path based upon detecting an error; a fault monitor circuit connected to said bus interface for monitoring operation of another processor module and for outputting a fault signal on a fourth data path; and a sub-processor connected to said third data path and to said fourth data path, said sub-processor outputting a stop signal to said bus interface to inhibit further operation of said bus interface and outputting a module fault signal to another processor module, upon receipt of one of said error signal and said fault signal.

Claim 18

A processor module for a multi-processor system with fault detection, the multi-processor system including a plurality of processor modules connected to a data bus, said processor module comprising: a starting circuit generating a first start signal and generating a second start signal delayed from said first start signal; a memory for storing data connected to a first data path; a bus interface connected to the data bus for transferring data between said data bus and said memory; a first processor connected to said first data path, having an input means for accepting said first start signal, for processing data stored in said memory, and for outputting a first output on said first data path; a second processor connected to a second data path having input means for accepting said second start signal so that operation of said second processor is delayed and overlapping in time with respect to the first processor, said second processor outputting a second output on said second data path which is delayed with respect to the first output; a comparator having means connected to said first data path for receiving the first output from the first processor, and means connected to said second data path for receiving the second output from the second processor, said comparator comparing said first output and said second output and outputting an error signal on a third data path based upon detecting an error; a fault monitor circuit connected to said bus interface for monitoring operation of another processor module and for outputting a fault signal on a fourth data path; and a sub-processor connected to said third data path and to said fourth data path, said sub-processor outputting a stop signal to said bus interface to inhibit further operation of said bus interface and outputting a module fault signal to another processor module, upon receipt of one of said error signal and said fault signal.

Claim 19

A processor module according to claim 11, wherein the comparator includes means for compensating for the time delay between data received from the first processor along the first data path and data received from the second processor along the second data path.