US5452418A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of using stream buffer to perform operation under normal operation mode and selectively switching to test mode to check data integrity during system operation
Assignee: Hewlett Packard Development Co LP
•
Filing: 1992-04-24
•
Granted: 1995-09-19
•
Expires: 2012-04-24
Abstract
Abstract The operation of a stream buffer varies depending on whether a normal operation mode or a test mode is selected. In the normal operation mode, the stream buffer is read from only when the data requested by a CPU read has been determined to reside there, and the stream buffer location read from is the location determined to contain the requested data. This determination is made by comparing the address of the read request with addresses of the data stored in the stream buffer. Also, the stream buffer is written with memory data in response to a read that misses the stream buffer, and the location written to is one that has been allocated to receive the incoming memory data. Two different buffer allocation methods are shown, first-in-first-out (FIFO) and least-recently-used (LRU). During the test operation mode, the stream buffer is written to and read from directly by the CPU at locations specified in the write and read requests, without regard to the data presence determination and the allocation that take place in the normal operation mode. The method provides a straightforward way of testing the stream buffer during system operation by bypassing some normal functions during test mode in favor of direct stream buffer access by the CPU.
Inventors
- 👤 David A. Tatosian
- 👤 Donald W. Smelser
- 👤 Paul M. Goodwin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 02:39
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1076; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0862; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/48; G06F2212/00; G06F2212/60; G06F2212/6022
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
353 words
A method of operating a stream buffer coupled between a central processor unit (CPU) and a memory, comprising the steps of: selecting between a normal operation mode and a test operation mode and dynamically switching between said normal operation mode and said test mode in various stages of system operation; performing the following steps during said normal operation mode: (1) upon receiving a memory write request from said CPU, writing data received from said CPU into said memory at a location indicated by said write request; and (2) upon receiving a memory read request from said CPU, performing the following steps: (A) determining whether the requested data resides in said stream buffer, and if so at what location therein; (B) if the requested data is determined to reside in said stream buffer, accessing said stream buffer at the determined location and returning the data contained therein to said CPU; and (C) if the requested data is determined not to reside in said stream buffer, performing the following steps: (i) accessing said memory at an address indicated by said read request and returning the data contained therein to said CPU; and (ii) accessing said memory at an address sequentially following the address indicated by said read request and writing the data contained therein to said stream buffer at an allocated location thereof; and performing the following steps during said test operation mode: (1) upon receiving a memory write request from said CPU, writing data received from said CPU into said stream buffer at a location indicated by said write request without regard to which location of said stream buffer would be allocated if said normal operation mode were presently selected; and (2) upon receiving a memory read request from said CPU, accessing said stream buffer at an address indicated by said read request and returning the data contained therein to said CPU without regard to either (a) whether said stream buffer would be determined to hold the requested data or (b) the location in said stream buffer that would be determined to hold the requested data if said normal operation mode were presently selected.
Claim 2
Independent Claim
353 words
A method of operating a stream buffer coupled between a central processor unit (CPU) and a memory, comprising the steps of: selecting between a normal operation mode and a test operation mode and dynamically switching between said normal operation mode and said test mode in various stages of system operation; performing the following steps during said normal operation mode: (1) upon receiving a memory write request from said CPU, writing data received from said CPU into said memory at a location indicated by said write request; and (2) upon receiving a memory read request from said CPU, performing the following steps: (A) determining whether the requested data resides in said stream buffer, and if so at what location therein; (B) if the requested data is determined to reside in said stream buffer, accessing said stream buffer at the determined location and returning the data contained therein to said CPU; and (C) if the requested data is determined not to reside in said stream buffer, performing the following steps: (i) accessing said memory at an address indicated by said read request and returning the data contained therein to said CPU; and (ii) accessing said memory at an address sequentially following the address indicated by said read request and writing the data contained therein to said stream buffer at an allocated location thereof; and performing the following steps during said test operation mode: (1) upon receiving a memory write request from said CPU, writing data received from said CPU into said stream buffer at a location indicated by said write request without regard to which location of said stream buffer would be allocated if said normal operation mode were presently selected; and (2) upon receiving a memory read request from said CPU, accessing said stream buffer at an address indicated by said read request and returning the data contained therein to said CPU without regard to either (a) whether said stream buffer would be determined to hold the requested data or (b) the location in said stream buffer that would be determined to hold the requested data if said normal operation mode were presently selected.
Claim 3
Dependent Claim
79 words
A method according to claim 1, wherein said determining step comprises the steps of: comparing a memory address accompanying said read request with the memory addresses of data blocks stored in said stream buffer; determining whether any of the comparisons result in a match, such a result indicating that the requested data resides in said stream buffer; and determining, based on which comparison resulted in a match, the location in said stream buffer at which the requested data resides.
Claim 4
Dependent Claim
69 words
A method according to claim 1, further comprising the step of: incrementing an allocation pointer after data is written to said stream buffer from said memory during said normal operation mode, the value of said allocation pointer indicating which location in said stream buffer is allocated to receive memory data upon a subsequent read request for which the request data is determined not to reside in said stream buffer.
Claim 5
Dependent Claim
74 words
A method according to claim 1, further comprising the step of: continually determining during said normal operation mode which location in said stream buffer has least recently been used to satisfy a CPU read request, the determined least-recently used location being taken as the location in said stream buffer that is allocated to receive memory data upon a read request for which the request data is determined not to reside in said stream buffer.
References Cited (Backward Citations)
US4292674A
Cited
US4621320A
Cited
US4601034A
Cited
US4761731A
Cited
US5133062A
Cited
US4835738A
Cited
US4951254A
Cited
US5301278A
Cited
US5003471A
Cited
US5146578A
Cited
US5261066A
Cited
US5337318A
Cited
US5241503A
Cited
US5289584A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |