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US5452251A
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Semiconductor memory device for selecting and deselecting blocks of word lines
Assignee: Fujitsu Ltd
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Filing: 1993-06-22
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Granted: 1995-09-19
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Expires: 2013-06-22
Abstract
Abstract A semiconductor memory device has 2 n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2 m (n>m) word lines among the 2 n word lines, and a second unit for not selecting a block of 2 k (m>k) word lines among the 2 m word lines. The second unit does not select the block of 2 k word lines, and selects a block of 2 k word lines prepared outside the 2 n word lines when any one of the 2 k word lines among the 2 m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.
Inventors
- 👤 Takao Akaogi
- 👤 Nobuaki Takashina
- 👤 Yasushi Kasa
- 👤 Kiyoshi Itano
- 👤 Hiromi Kawashima
- 👤 Minoru Yamashita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:33
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C16/00; G11C16/02; G11C16/06; G11C16/08; G11C16/10; G11C16/107; G11C16/12; G11C16/14; G11C16/16; G11C16/26; G11C16/30; G11C16/34; G11C16/3404; G11C16/3409; G11C16/3436; G11C16/344; G11C16/3445; G11C16/3454; G11C16/3459; G11C16/3468; G11C16/3472; G11C16/3481; G11C29/02; G11C29/028; G11C29/04; G11C29/08; G11C29/12; G11C29/18; G11C29/30; G11C29/34; G11C29/46; G11C29/50; G11C29/50004; G11C29/802; G11C29/816; G11C29/82; G11C5/00; G11C5/14; G11C5/145; G11C7/00; G11C7/06; G11C7/067; G11C8/00; G11C8/08; G11C8/10; G11C16/04; G11C16/0408; G11C16/0416; G11C2029/5004; G11C29/88
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
186 words
A semiconductor memory device comprising: 2 n word lines; a plurality of bit lines; a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable; a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines; a sense amplifier for reading data out of said memory cells; a first means for simultaneously selecting a block of 2 m word lines among said 2 n word lines, wherein n is greater than m; and a second means for deselecting a first block of 2 k word lines of said 2 m word lines, wherein m is greater than k, said second means deselecting said first block of 2 k word lines and selecting a second block of 2 k word lines prepared outside said 2 n word lines when any one of said first block of 2 k word lines among said 2 m word lines is defective.
Claim 2
Dependent Claim
186 words
A semiconductor memory device comprising: 2 n word lines; a plurality of bit lines; a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable; a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines; a sense amplifier for reading data out of said memory cells; a first means for simultaneously selecting a block of 2 m word lines among said 2 n word lines, wherein n is greater than m; and a second means for deselecting a first block of 2 k word lines of said 2 m word lines, wherein m is greater than k, said second means deselecting said first block of 2 k word lines and selecting a second block of 2 k word lines prepared outside said 2 n word lines when any one of said first block of 2 k word lines among said 2 m word lines is defective.
Claim 3
Dependent Claim
29 words
A semiconductor memory device as claimed in claim 1, wherein said selected word lines receive a negative voltage, and said unselected word lines receive a zero or positive voltage.
Claim 4
Dependent Claim
55 words
A semiconductor memory device as claimed in claim 1, wherein said block of 2 n word lines forms a real cell block, said block of 2 m word lines forms an erase block, and said second block of 2 k word lines outside said block of 2 n word lines forms a redundant cell block.
Claim 5
Dependent Claim
20 words
A semiconductor memory device as claimed in claim 1, wherein said semiconductor memory device is constituted by a flash memory.
Claim 6
Dependent Claim
214 words
A semiconductor memory device comprising: 2 n word lines; a plurality of bit lines; a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable; a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines; a sense amplifier for reading data out of said memory cells; a first means for simultaneously selecting a block of 2 m word lines among said 2 n word lines, wherein n is greater than m; and a second means for deselecting a first block of 2 k word lines among said 2 m word lines, wherein m is greater than k, wherein data being written to any memory cell transistor, which is contained in said 2 k word lines and whose threshold voltage is lower than the potential of an unselected word line before the data are written, so that the threshold voltage of said memory cell transistor exceeds the potential of said unselected word line, and a second block of 2 k word lines prepared outside said 2 n word lines is used as redundant word lines.
Claim 7
Dependent Claim
214 words
A semiconductor memory device comprising: 2 n word lines; a plurality of bit lines; a plurality of nonvolatile memory cells each formed of a MIS transistor disposed at each intersection of said word lines and said bit lines, and a threshold voltage of said MIS transistor being externally electrically controllable; a write circuit for writing data to a memory cell located at an intersection of selected ones of said word lines and said bit lines; a sense amplifier for reading data out of said memory cells; a first means for simultaneously selecting a block of 2 m word lines among said 2 n word lines, wherein n is greater than m; and a second means for deselecting a first block of 2 k word lines among said 2 m word lines, wherein m is greater than k, wherein data being written to any memory cell transistor, which is contained in said 2 k word lines and whose threshold voltage is lower than the potential of an unselected word line before the data are written, so that the threshold voltage of said memory cell transistor exceeds the potential of said unselected word line, and a second block of 2 k word lines prepared outside said 2 n word lines is used as redundant word lines.
Claim 8
Dependent Claim
20 words
A semiconductor memory device as claimed in claim 5, wherein said semiconductor memory device is constituted by a flash memory.
References Cited (Backward Citations)
US5297148A
Cited
US5233559A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-18 | 1999-03-20 | 1999-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-18 | 2003-03-20 | 2003-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-18 | 2007-03-20 | 2007-09-19 | $7700.00 | Window Closed / Lapsed |