High power, compound semiconductor device and fabrication process

Claim 2

A III-V compound semiconductor device comprising, a semi-insulating III-V compound semiconductor substrate, a compound semiconductor etch stop layer on a front surface of said substrate, said etch stop layer characterized by an etch rate that is substantially slower than an etch rate of said substrate, an undoped compound semiconductor buffer layer on said etch stop layer, plural layers of compound semiconductor material formed on said buffer layer, said plural layers forming at least one active semiconductor device, said active semiconductor device having heat generating regions associated therewith, said substrate having wells formed in a back surface thereof, said wells being located in said substrate proximate to said heat generating regions in said plural layers, said wells in said substrate characterized by at least two different depths such that deepest portions of said wells having a distance of 0.2 to less than 5 microns from the nearest parts of said heat generating regions, and a thermally conductive material disposed in said wells.

Claim 3

The device of claim 1 wherein said substrate is composed of gallium arsenide.

Claim 4

The device of claim 1 wherein said etch stop layer is composed of aluminum gallium arsenide.

Claim 5

The device of claim 3 wherein said etch stop layer is composed of Al x Ga 1-x As, where x<0.3.

Claim 6

The device of claim 1 wherein said buffer layer is composed of undoped gallium arsenide.

Claim 7

The device of claim 1 wherein said etch stop layer has a thickness in a range of 0.1-10 μm.

Claim 8

The device of claim 6 wherein said thickness is in a range of 0.2-1.0 μm.

Claim 9

The device of claim 1 wherein said buffer layer has a thickness in a range of 0.2-10 μm.

Claim 10

The device of claim 8 wherein said thickness is in a range of 2-3 μm.

Claim 11

The device of claim 1 wherein said active semiconductor device formed in said plural layers is a field effect transistor.

Claim 12

The device of claim 1 wherein said active semiconductor device formed in said plural layers is a heterojunction bipolar transistor.

Claim 13

The device of claim 1 wherein said plural layers of compound semiconductor material form an integrated circuit.

Claim 14

A III-V compound semiconductor device comprising, a semi-insulating III-V compound semiconductor substrate, a compound semiconductor etch stop layer on a front surface of said substrate, said etch stop layer characterized by an etch rate that is substantially slower than an etch rate of said substrate, an undoped compound semiconductor buffer layer on said etch stop layer, plural layers of compound semiconductor material formed on said buffer layer, said plural layers forming at least one active semiconductor device, said active semiconductor device having heat generating regions associated therewith, said substrate having wells formed in a back surface thereof, said wells being located in said substrate proximate to said heat generating regions in said plural layers, said wells in said substrate characterized by at least two different depths such that deepest portions of said wells have a distance of 0.2 to less than 5 microns from the nearest parts of the heat generating regions, and wherein said wells formed in said substrate have depths under drain electrodes of said at least one active semiconductor device which are less than depths of said wells under source electrodes and drain-to-source channels of said at least one active semiconductor device, such that a heat conduction pathlength from said drain electrodes to said heat conducting material is larger than a heat conduction pathlength from said source electrodes and said drain-to-source channels to said heat conducting material.

Claim 15

A III-V compound semiconductor device comprising, a semi-insulating III-V compound semiconductor substrate, a compound semiconductor etch stop layer on a front surface of said substrate, said etch stop layer characterized by an etch rate that is substantially slower than an etch rate of said substrate, an undoped compound semiconductor buffer layer on said etch stop layer, plural layers of compound semiconductor material formed on said buffer layer, said plural layers forming at least one active semiconductor device, said active semiconductor device having heat generating regions associated therewith, said substrate having wells formed in a back surface thereof, said wells being located in said substrate proximate to said heat generating regions in said plural layers, said wells in said substrate characterized by at least two different depths such that deepest portions of said wells have a distance of 0.2 to less than 5 microns from the nearest parts of the heat generating regions, and wherein said wells formed in said substrate have depths under drain electrodes of said at least one active semiconductor device which are less than depths of said wells under source electrodes and drain-to-source channels of said at least one active semiconductor device, such that a heat conduction pathlength from said drain electrodes to said heat conducting material is larger than a heat conduction pathlength from said source electrodes and said drain-to-source channels to said heat conducting material.

Claim 16

The device of claim 13 wherein said heat conduction pathlength for said drain electrodes is about 10-40 μm larger than said heat conduction pathlength for said source electrodes and said drain-to-source channels.