US4189688A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microwave FET power oscillator
Assignee: RCA Corp
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Filing: 1978-07-24
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Granted: 1980-02-19
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Expires: 1998-07-24
Abstract
Abstract First and second field effect transistors (FETs) each have a gallium arsenide substrate with an N-type active region that carries first and second electrodes in ohmic contact therewith and a gate electrode. The FETs are mounted in a flip-chip carrier that connects the first electrodes to ground. The FETs are biased to cause a current to flow from the first to second electrodes, whereby the first and second electrodes serve as drains and sources, respectively, of the FETs. The gate of the first FET is connected to a resonator. Additionally, a matching network connects the source of the first FET to the gate of the second FET. The matching network and the biasing of the first FET cause the gate input impedance thereof to be of a negative value that compensates for losses in the resonator. A load connected to the source of the second FET and the bias voltage cause the second FET to have a gate input impedance of a negative value that causes oscillation.
Inventors
- 👤 Franco N. Sechi
- 👤 Raymond L. Camisa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 02:52
CPC Classifications
H; H03; H03B; H03B5/00; H03B5/18; H03B5/1841; H03B5/1847; H03B5/1852; H03B2200/00; H03B2200/003; H03B2200/0034; H03B2201/00; H03B2201/02; H03B2201/0208; H03B5/02; H03B5/04
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
230 words
In an oscillator circuit wherein first and second field effect transistors each have pluralities of unit sources, unit drains and unit gates disposed upon a semiconductor substrate, a heat sink connecting said unit sources to ground, the improvement comprising: means for applying a bias voltage to said first and second transistors for causing a higher interelectrode capacitance between respective unit gates and unit drains thereof than between respective unit gates and unit sources thereof, said unit gates, unit drains and unit sources of said first transistor and second transistor serving as gate, source and drain electrodes, respectively; a resonator connected between the gate electrode of said first transistor and the respective drain electrodes of said first and second transistors; coupling means for coupling the source electrode of said first transistor to the gate electrode of said second transistor, said coupling means and said bias voltage causing the gate input impedance of said first transistor to be of a negative value, said resonator, said first transistor and said coupling means forming a composite network with a Q higher than the Q of said resonator; and load means connected to the source electrode of said second transistor, said load means and said bias voltage causing the gate input impedance of said second transistor to be of a negative value such that said load means, said composite network and said second transistor oscillate.
Claim 2
Dependent Claim
230 words
In an oscillator circuit wherein first and second field effect transistors each have pluralities of unit sources, unit drains and unit gates disposed upon a semiconductor substrate, a heat sink connecting said unit sources to ground, the improvement comprising: means for applying a bias voltage to said first and second transistors for causing a higher interelectrode capacitance between respective unit gates and unit drains thereof than between respective unit gates and unit sources thereof, said unit gates, unit drains and unit sources of said first transistor and second transistor serving as gate, source and drain electrodes, respectively; a resonator connected between the gate electrode of said first transistor and the respective drain electrodes of said first and second transistors; coupling means for coupling the source electrode of said first transistor to the gate electrode of said second transistor, said coupling means and said bias voltage causing the gate input impedance of said first transistor to be of a negative value, said resonator, said first transistor and said coupling means forming a composite network with a Q higher than the Q of said resonator; and load means connected to the source electrode of said second transistor, said load means and said bias voltage causing the gate input impedance of said second transistor to be of a negative value such that said load means, said composite network and said second transistor oscillate.
Claim 3
Dependent Claim
113 words
The oscillator circuit of claim 1 wherein said load means comprises: a third field effect transistor having pluralities of unit sources, unit drains and unit gates disposed upon a semiconductor substrate, the unit sources of said third transistor being connected to a heat sink; and further comprising: means for applying a bias voltage to said third transistor for causing a higher interelectrode capacitance between unit gates and unit sources thereof than between unit gates and unit drains of said third transistor, unit gates, unit drains and unit sources of said third transistor serving as gate, drain and source electrodes, respectively, said load means being connected to the drain electrode of said third transistor.
Claim 4
Dependent Claim
15 words
The oscillator circuit of claim 1 wherein said coupling means includes a microstrip transmission line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1983-02-18 | 1983-08-20 | 1984-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1987-02-18 | 1987-08-20 | 1988-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1991-02-18 | 1991-08-20 | 1992-02-19 | $7700.00 | Window Closed / Lapsed |