US5448709A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Disk array controller having command descriptor blocks utilized by bus master and bus slave for respectively performing data transfer operations
Assignee: Hewlett Packard Development Co LP
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Filing: 1992-10-13
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Granted: 1995-09-05
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Expires: 2012-10-13
Abstract
Abstract A disk array controller board which utilizes an EISA bus master which is a slave on its internal data bus to allow an advanced drive array controller chip (ADAC) to operate as a master. The ADAC is connected to transfer buffer RAM. The protocol of the internal data bus provides for a cycles to load a host memory address into the bus slave, to provide transfer count information and slave specific information and for a series of data transfer cycles. The local processor is connected to the EISA bus master and the ADAC to control operations and to provide certain information. The ADAC is controlled by structures referred to as command descriptor blocks (CDBs). Each CDB includes information which describes the various addresses, control bits and functional bits used by the ADAC to perform its transfer operations. The local processor directly writes and deposits data forming a CDB into the transfer buffer RAM. The ADAC obtains the CDB, loads the data into registers and then performs operations according to the information contained in these registers until a transfer is done. The ADAC itself performs operations, including automatic stripe scattering and gathering to develop contiguous host memory fields from striped array data. A series of CDBs can be chained so that a complex series of tasks can be developed. In one variation a string of CDBs is developed to transfer data but some data is transferred to the bit bucket, while other data is actually transferred.
Inventors
- 👤 Gregory T. Chandler
- 👤 Thomas W. Grieff
- 👤 Ryan A. Callison
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:36
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F3/0668; G06F3/0671; G06F3/0673
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
317 words
A disk drive array controller for use with a plurality of disk drives forming an array and for installation in a host computer, the controller comprising: local processor means for controlling operation of the disk drive array controller; unitary buffer memory means for temporarily storing disk drive and command data; means for transferring data between the disk drives and said buffer memory means, said means for transferring data between the disk drives and said buffer memory means connected to said local processor means for receiving control information; and means for transferring data between said buffer memory means and the host computer, said means for transferring data between said buffer memory means and the host computer including: a bus for transferring host address information and data; bus slave means connected to said bus and to the host computer for receiving said host address information and transferring data between said bus and the host computer; and bus master means connected to said bus and said buffer memory means for providing said host address information to said bus and transferring data between said bus and said buffer memory means, wherein said bus master means includes: a plurality of registers for receiving information indicative of the transfer to be performed; means for controlling the transfer according to information contained in said register; and means for loading said registers with data forming a command descriptor block from said buffer memory means; wherein the bus master is connected to the local processor and further includes a register for receiving from the local processor an address in the buffer memory means pointing to the command descriptor block and means for initiating said means for loading the registers after receiving said address of the command descriptor block in said register; wherein said local processor is coupled to said buffer memory means and includes means for depositing the command descriptor block in the buffer memory means.
Claim 2
Dependent Claim
317 words
A disk drive array controller for use with a plurality of disk drives forming an array and for installation in a host computer, the controller comprising: local processor means for controlling operation of the disk drive array controller; unitary buffer memory means for temporarily storing disk drive and command data; means for transferring data between the disk drives and said buffer memory means, said means for transferring data between the disk drives and said buffer memory means connected to said local processor means for receiving control information; and means for transferring data between said buffer memory means and the host computer, said means for transferring data between said buffer memory means and the host computer including: a bus for transferring host address information and data; bus slave means connected to said bus and to the host computer for receiving said host address information and transferring data between said bus and the host computer; and bus master means connected to said bus and said buffer memory means for providing said host address information to said bus and transferring data between said bus and said buffer memory means, wherein said bus master means includes: a plurality of registers for receiving information indicative of the transfer to be performed; means for controlling the transfer according to information contained in said register; and means for loading said registers with data forming a command descriptor block from said buffer memory means; wherein the bus master is connected to the local processor and further includes a register for receiving from the local processor an address in the buffer memory means pointing to the command descriptor block and means for initiating said means for loading the registers after receiving said address of the command descriptor block in said register; wherein said local processor is coupled to said buffer memory means and includes means for depositing the command descriptor block in the buffer memory means.
Claim 3
Dependent Claim
33 words
The controller of claim 1, wherein said bus master means further includes means for writing the values in said plurality of registers back to said buffer memory means after completion of the transfer.
Claim 4
Dependent Claim
39 words
The controller of claim 2, wherein said bus master means further includes means for providing an address pointing to the location following the loaded command descriptor block to said command descriptor block address register after completion of the transfer.
Claim 5
Dependent Claim
61 words
The controller of claim 3, wherein said registers include a bit indicating a last command descriptor block and wherein said bus master means-further includes means for initiating said means for loading after said location following address is provided to said command descriptor block address register if said last command descriptor block bit is not set in the loaded command descriptor block.
Claim 6
Dependent Claim
40 words
The controller of claim 4, wherein said registers include a bit indicating a transfer no recipient and wherein said bus master means includes means for transferring data from said buffer memory means to no recipient when said bit is set.
Claim 7
Dependent Claim
106 words
The controller of claim 1, wherein said registers include a register for receiving a starting memory address in said host memory, a register for receiving a host memory offset value equal to a data stripe size, a register for receiving a stripe size indicating the data in a stripe portion contained on a single disk and a register for counting the amount of data transferred, and wherein said bus master means includes means for adding said host memory offset value to said starting memory address when the amount of data transferred equals the stripe size and means for issuing this address to said bus slave means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |