EP0503936A1
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EP
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Control system for a storage disk array
Assignee: NCR International Inc
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Filing: 1992-03-12
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Granted: —
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Expires: 2012-03-12
Abstract
Abstract An interrupt signal indicating the existence of a bus configuration error within a disk array system is generated by monitoring enable signals (EN1-EN4) controlling bus drivers (31,101,121,141) included in the array system. The array configuration error detector includes a bus configuration error detector (171-175) for each multiple-source bus (21-25) within the array. Each bus configuration error detector e.g. 171) is connected to receive all enable signals (EN1-EN4) for the bus drivers (31,101,121,141) associated with one bus (e.g. 21) and decode the received enable signals to generate an error signal when more than one of the received enable signals (EN1-EN4) is active. The error signals generated for each of the data busses (21-25) are provided to an adder (180) and combined to form the configuration error interrupt signal for the array.
Inventors
- 👤 Mahmoud K. Jibbe
- 👤 Craig C. Mccombs
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 12:33
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0745; G06F11/0727; G06F11/0793
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
156 words
A control system for a storage disk array, including a plurality of data busses (21-25) associated with respective disk drives and a plurality of bus drivers (31,101,121,141) associated with each one of said data busses (21), characterized by: a bus configuration error detector circuit (171) corresponding to each one of said data busses (21), each one of said error detector circuits (171) being adapted to generate a bus configuration interrupt signal for its corresponding data bus (21) when more than one of the bus drivers (31,101,121,141) associated with the corresponding data bus (21) is in an enabled state; and combining means (180,190) connected to receive the bus configuration interrupt signals generated by each of said bus configuration error detector circuits (171-175) and adapted to combine the interrupt signals to generate an array configuration interrupt signal, said array configuration interrupt signal indicating the detection of a configuration error in at least one of said data busses (21-25).
Claim 2
Dependent Claim
105 words
A system according to claim 1, characterized in that each one of said bus drivers (31,101,121,141) is enabled in response to an associated binary enable signal (EN1-EN4), each of said enable signals (EN1-EN4) having a first state enabling its associated bus driver (31,101,121,141) to provide data to its associated array bus (21) and having a second state disabling its associated bus driver (31,101,121,141); and in that each one of said bus configuration error detector circuits (171) includes decoding means (231-235,240-244) connected to receive the enable signals (EN1-EN4) for the bus drivers (31,101,121,141) associated with the data bus (21) corresponding to that error detector circuit (171).
Claim 3
Dependent Claim
106 words
A system according to claim 2, characterized in that each of said decoding means (231-235,240-244) includes: an inverter (231-235) associated with each enable signal (EN1-EN4) received by the decoding means (231-235,240-244); an AND gate (241-244) associated with each enable signal (EN1-EN4) received by the decoding means (231-235,240-244), each one of said AND gates (241-244) being connected to receive its associated enable signal (EN1-EN4) and the inverse of the remaining enable signals (EN1-EN4); an AND gate (240) connected to receive the output signals from each of said inverters (231-235); and a NOR gate (249) connected to receive the output signals from each of said AND gates (240-244).
Claim 4
Independent Claim
39 words
A system according to any one of the preceding claims, characterized in that said combining means includes filtering means (190) connected to receive said array configuration interrupt signal for suppresing temporary signal transients in said array configuration interrupt signal.
Claim 5
Independent Claim
74 words
A system according to any one of claims 2 to 4, characterized by: a register (161-165) corresponding to each one of said data busses (21-25) and connected to receive and hold the enable signals (EN1-EN4) for the bus drivers (31,101,121,141) associated with its corresponding data bus, wherein each one of said bus configuration error detector circuits (171) is connected to receive the enable signals (EN1-EN4) stored in a corresponding one of said registers (161).
Claim 6
Independent Claim
141 words
A method of controlling a storage disk array including a plurality of data busses (21-25), each of said data busses (21-25) having a plurality of bus drivers, (31,101,121,141) characterized by the steps of: for each one of said plurality of data busses (21-25): determining the enablement state of each one of said plurality of bus drivers (31,101,121,141) associated with said data bus (21); generating a bus configuration interrupt signal for said data bus (21) when more than one of said plurality of bus drivers (31,101,121,141) associated with said data bus (21) is in an enabled state; and combining the bus configuration interrupt signals for each one of said plurality of data busses (21-25) to generate an array configuration interrupt signal, said array configuration interrupt signal indicating the detection of a configuration error in at least one of said data busses (21-25).
References Cited (Backward Citations)
US4945540A
Cited
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