Patent US5448185A successfully refreshed from Google Patents.
US5448185A
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US
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Programmable dedicated FPGA functional blocks for multiple wide-input functions
Assignee: Microsemi SoC Corp
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Filing: 1993-10-27
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Granted: 1995-09-05
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Expires: 2013-10-27
Abstract
Abstract According to the present invention, a plurality of programmable multi-bit output functional block modules, each capable of assuming the functionality of one of the set of adders, subtracters, magnitude comparators, identity comparators, up/down counters, registers, multi-bit ANDs, and similar devices, are placed in predetermined locations of the FPGA chip. The number of functional blocks is much fewer than the number of FPGA modules on the chip. Each of the functional blocks has a plurality of inputs and outputs, each of which is capable of being connected to the neighboring programmable interconnect resources. Communication between and amongst functional blocks is carried out with the standard programmable resources available on board the FPGA chip.
Inventors
- 👤 Sinan Kaptanoglu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:21
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/57; G06F7/575; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17736; H03K19/17744; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3896
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
147 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules, each of said FPGA logic modules including I inputs and J outputs; a plurality of functional block modules, each of said functional block modules including K inputs and L outputs, wherein K>I and L>J; said K inputs of each of said functional block modules including a first N-bit parallel input data bus and a second N-bit parallel input data bus and said L outputs of each of said functional block modules including an N-bit parallel output data bus wherein K≧2N and L≧N and N≧2 and wherein said functional block modules perform combinatorial operations on said first N-bit parallel input data bus and said second N-bit parallel input data bus in parallel to form an N-bit parallel output on said N-bit parallel output data bus.
Claim 2
Dependent Claim
147 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules, each of said FPGA logic modules including I inputs and J outputs; a plurality of functional block modules, each of said functional block modules including K inputs and L outputs, wherein K>I and L>J; said K inputs of each of said functional block modules including a first N-bit parallel input data bus and a second N-bit parallel input data bus and said L outputs of each of said functional block modules including an N-bit parallel output data bus wherein K≧2N and L≧N and N≧2 and wherein said functional block modules perform combinatorial operations on said first N-bit parallel input data bus and said second N-bit parallel input data bus in parallel to form an N-bit parallel output on said N-bit parallel output data bus.
Claim 3
Dependent Claim
112 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules, each of said FPGA logic modules including I inputs and J outputs; a plurality of functional block modules, each of said functional block modules including K inputs and L outputs, wherein K>I and L>J, said functional block modules adapted for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform combinatorial functions including counter and comparator.
Claim 4
Dependent Claim
112 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules, each of said FPGA logic modules including I inputs and J outputs; a plurality of functional block modules, each of said functional block modules including K inputs and L outputs, wherein K>I and L>J, said functional block modules adapted for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform combinatorial functions including counter and comparator.
Claim 5
Dependent Claim
32 words
The user programmable FPGA architecture according to claim 2 wherein said functional block modules are programmable to perform said combinatorial functions based upon the states of a subset of said K inputs.
Claim 6
Dependent Claim
221 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules, each of said FPGA logic modules including I inputs and J outputs; a plurality of functional block modules, each of said functional block modules including K inputs and L outputs, wherein K>I and L>J; said K inputs of each of said functional block modules including a first N-bit parallel input data bus and a second N-bit parallel input data bus and said L outputs of each of said functional block modules including an N-bit parallel output data bus wherein K≧2N and L≧N and N≧2 and wherein said functional block modules perform combinatorial operations on said first N-bit parallel input data bus and said second N-bit parallel input data bus in parallel to form an N-bit parallel output on said N-bit parallel output data bus; said functional block modules each including an N-bit adder operatively connected to said first N-bit parallel input data bus and said second N-bit parallel input data bus, and an N-bit adder parallel output bus operatively connected to both an N+1 bit adder and an array of N 2-bit multiplexers; wherein each of said functional block modules is independently programmable to perform one of the functions selected from the group of adder and AND gate.
Claim 7
Dependent Claim
221 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules, each of said FPGA logic modules including I inputs and J outputs; a plurality of functional block modules, each of said functional block modules including K inputs and L outputs, wherein K>I and L>J; said K inputs of each of said functional block modules including a first N-bit parallel input data bus and a second N-bit parallel input data bus and said L outputs of each of said functional block modules including an N-bit parallel output data bus wherein K≧2N and L≧N and N≧2 and wherein said functional block modules perform combinatorial operations on said first N-bit parallel input data bus and said second N-bit parallel input data bus in parallel to form an N-bit parallel output on said N-bit parallel output data bus; said functional block modules each including an N-bit adder operatively connected to said first N-bit parallel input data bus and said second N-bit parallel input data bus, and an N-bit adder parallel output bus operatively connected to both an N+1 bit adder and an array of N 2-bit multiplexers; wherein each of said functional block modules is independently programmable to perform one of the functions selected from the group of adder and AND gate.
Claim 8
Dependent Claim
142 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform one of the functions selected from the group of adder, subtracter, up-counter, down-counter, magnitude comparator, identity comparator, register, inverting register, AND gate, and decoder, said functional block modules including an N-bit adder operatively connected to said first N-bit input data bus and said second N-bit input data bus, and an N-bit adder output bus operatively connected to both an N+1 bit adder and an array of N 2-bit multiplexers.
Claim 9
Dependent Claim
142 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform one of the functions selected from the group of adder, subtracter, up-counter, down-counter, magnitude comparator, identity comparator, register, inverting register, AND gate, and decoder, said functional block modules including an N-bit adder operatively connected to said first N-bit input data bus and said second N-bit input data bus, and an N-bit adder output bus operatively connected to both an N+1 bit adder and an array of N 2-bit multiplexers.
Claim 10
Dependent Claim
197 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform one of the functions selected from the group of adder, subtracter, up-counter, down-counter, magnitude comparator, identity comparator, register, inverting register, AND gate, and decoder, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit adder operatively connected to said first N-bit multiplexer output and said second N-bit multiplexer output, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a third array of N 2-bit multiplexers.
Claim 11
Dependent Claim
197 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform one of the functions selected from the group of adder, subtracter, up-counter, down-counter, magnitude comparator, identity comparator, register, inverting register, AND gate, and decoder, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit adder operatively connected to said first N-bit multiplexer output and said second N-bit multiplexer output, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a third array of N 2-bit multiplexers.
Claim 12
Dependent Claim
255 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform one of the functions selected from the group of adder, subtracter, up-counter, down-counter, magnitude comparator, identity comparator, register, inverting register, AND gate, and decoder, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit inverter having an inverter input and an inverter output, said inverter input operatively connected to said second N-bit multiplexer output, a third array of N 2-bit multiplexers having a first input connected to said inverter output, a second input connected to said second N-bit multiplexer output, and an N-bit output, an N-bit adder operatively connected to said first N-bit multiplexer output and said N-bit output of said third array of N 2-bit multiplexers, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a fourth array of N 2-bit multiplexers.
Claim 13
Dependent Claim
255 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform one of the functions selected from the group of adder, subtracter, up-counter, down-counter, magnitude comparator, identity comparator, register, inverting register, AND gate, and decoder, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit inverter having an inverter input and an inverter output, said inverter input operatively connected to said second N-bit multiplexer output, a third array of N 2-bit multiplexers having a first input connected to said inverter output, a second input connected to said second N-bit multiplexer output, and an N-bit output, an N-bit adder operatively connected to said first N-bit multiplexer output and said N-bit output of said third array of N 2-bit multiplexers, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a fourth array of N 2-bit multiplexers.
Claim 14
Dependent Claim
121 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform a combinatorial operation, said functional block modules including an N-bit adder operatively connected to said first N-bit input data bus and said second N-bit input data bus, and an N-bit adder output bus operatively connected to both an N+1 bit adder and an array of N 2-bit multiplexers.
Claim 15
Dependent Claim
121 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform a combinatorial operation, said functional block modules including an N-bit adder operatively connected to said first N-bit input data bus and said second N-bit input data bus, and an N-bit adder output bus operatively connected to both an N+1 bit adder and an array of N 2-bit multiplexers.
Claim 16
Dependent Claim
176 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform a combinatorial operation, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit adder operatively connected to said first N-bit multiplexer output and said second N-bit multiplexer output, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a third array of N 2-bit multiplexers.
Claim 17
Dependent Claim
176 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform a combinatorial operation, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit adder operatively connected to said first N-bit multiplexer output and said second N-bit multiplexer output, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a third array of N 2-bit multiplexers.
Claim 18
Dependent Claim
234 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform a combinatorial operation, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit inverter having an inverter input and an inverter output, said inverter input operatively connected to said second N-bit multiplexer output, a third array of N 2-bit multiplexers having a first input connected to said inverter output, a second input connected to said second N-bit multiplexer output, and an N-bit output, an N-bit adder operatively connected to said first N-bit multiplexer output and said N-bit output of said third array of N 2-bit multiplexers, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a fourth array of N 2-bit multiplexers.
Claim 19
Dependent Claim
234 words
A user programmable FPGA architecture disposed on an integrated circuit, said architecture comprising: a general interconnect structure; a plurality of FPGA logic modules; a plurality of functional block modules for performing combinatorial operations on a first N-bit data word and a second N-bit data word, for N≧2, provided by a corresponding first N-bit input data bus and a second N-bit input data bus, each of said functional block modules independently programmable to perform a combinatorial operation, said functional block modules including a first array of N 2-bit multiplexers having an input connected to said first N-bit input data bus and an output connected to a first N-bit multiplexer output, a second array of N 2-bit multiplexers having an input connected to said second N-bit input data bus and an output connected to a second N-bit multiplexer output, an N-bit inverter having an inverter input and an inverter output, said inverter input operatively connected to said second N-bit multiplexer output, a third array of N 2-bit multiplexers having a first input connected to said inverter output, a second input connected to said second N-bit multiplexer output, and an N-bit output, an N-bit adder operatively connected to said first N-bit multiplexer output and said N-bit output of said third array of N 2-bit multiplexers, and an N-bit adder output bus operatively connected to both an N+1 bit adder and a fourth array of N 2-bit multiplexers.
Claim 20
Dependent Claim
11 words
A user programmable FPGA architecture according to claim 1 wherein N≧4.
Claim 21
Dependent Claim
11 words
A user programmable FPGA architecture according to claim 1 wherein N≧8.
Claim 22
Dependent Claim
61 words
A user programmable FPGA architecture according to claim 1 wherein each of said functional block modules further comprises: an N-bit adder operatively connected to said first N-bit parallel input data bus and said second N-bit parallel input data bus, and an N-bit adder parallel output bus operatively connected to both an N+1 bit adder and an array of N 2-bit multiplexers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |