Patent EP0234922A2 successfully refreshed from Google Patents.
US5448014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mass simultaneous sealing and electrical connection of electronic devices
Assignee: Northrop Grumman Systems Corp
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Filing: 1993-01-27
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Granted: 1995-09-05
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Expires: 2013-01-27
Abstract
Abstract The present invention provides a new and effective method for the sealing and electrical testing of electronic devices; and particularly for surface acoustic wave devices. In accordance with the present invention, the cost and size of making hermetically sealed packages for electronic devices and of electrically testing each device is significantly reduced over the prior art by making use of mass simultaneous sealing and electrical connection at the wafer level, and by using substrates with hermetically sealed and electrically conductive via holes. Further, cost reduction is effected by making use of final electrical testing with wafer probe test techniques before dicing.
Inventors
- 👤 Alvin M. Kong
- 👤 James C. Lau
- 👤 Steven S. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:26
CPC Classifications
H; H03; H03H; H03H9/00; H03H9/02; H03H9/05; H03H9/058; H03H9/059; H03H9/10; H03H9/1064; H03H9/1071; H10; H10W; H10W90/00; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/4913
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
104 words
A method of mass sealing and testing electronic devices, comprising the steps of: (a) initially aligning a cover wafer having a plurality of electrically conductive elements therein over a plurality of individual electronic devices supported at a single substrate (b) next both: (i) sealing each electronic device by bonding the aligned cover wafer against the substrate wafer; and, (ii) forming an electrical communication between the electrically conductive elements in the cover wafer and the electronic devices supported at the substrate wafer; and, (c) finally testing the plurality of sealed electronic devices; wherein steps (b)(i) and (b)(ii) both take place while at the wafer level.
Claim 2
Independent Claim
104 words
A method of mass sealing and testing electronic devices, comprising the steps of: (a) initially aligning a cover wafer having a plurality of electrically conductive elements therein over a plurality of individual electronic devices supported at a single substrate (b) next both: (i) sealing each electronic device by bonding the aligned cover wafer against the substrate wafer; and, (ii) forming an electrical communication between the electrically conductive elements in the cover wafer and the electronic devices supported at the substrate wafer; and, (c) finally testing the plurality of sealed electronic devices; wherein steps (b)(i) and (b)(ii) both take place while at the wafer level.
Claim 3
Dependent Claim
32 words
The method of claim 1 further comprising a step, subsequent to step (c), of dicing the wafer-level bonded wafers into a plurality of individual sealed packages each containing a tested electronic device.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein step (c) includes a wafer probe electrical testing technique.
Claim 5
Dependent Claim
28 words
The method of claim 1 wherein the cover wafer comprises an electrically nonconductive material having thermal expansion characteristics similar to the thermal expansion characteristics of the substrate wafer.
Claim 6
Dependent Claim
17 words
The method of claim 4 wherein the substrate wafer is quartz and the cover wafer is glass-ceramic.
Claim 7
Dependent Claim
23 words
The method of claim 4 wherein sealing step (b)(i) results in the formation of a hermetic seal about each of the electronic devices.
Claim 8
Dependent Claim
33 words
The method of claim 6 wherein the plurality of electrically conductive elements in the cover wafer comprise hermetically sealed conductive vias which are adapted to connect the electronic devices to external electrical terminals.
Claim 9
Dependent Claim
68 words
The method of claim 1 wherein the sealing step (b)(i) is carried out at a relatively low temperature and during which step the cover wafer is attached to the substrate wafer by a grid of solder strips patterned about each electrical device; wherein patterning of the grid is carried out prior to the sealing step (b)(i); and wherein said relatively low temperature is less than 200 degrees Celsius.
Claim 10
Dependent Claim
22 words
The method of claim 8 wherein the grid of solder strips maintains a separation between the substrate wafer and the cover wafer.
Claim 11
Dependent Claim
22 words
The method of claim 8 wherein the sealing step (b) (i) results in the formation of a hermetic solid liquid interdiffusion bond.
Claim 12
Dependent Claim
50 words
The method of claim 10 wherein the hermetic solid liquid interdiffusion bond is formed between a gold grid patterned upon one of the wafers and an indium grid patterned upon the other of the two wafers; wherein patterning of the grids is carried out prior to the sealing step (b)(i).
Claim 13
Dependent Claim
26 words
The method of claim 8 wherein the recited dicing step comprises dicing the bonded and tested wafers down center lines of the grid of solder strips.
Claim 14
Dependent Claim
18 words
The method of claim 12 wherein the seal formed by the sealing step (b)(i) is a hermetic seal.
Claim 15
Dependent Claim
14 words
The method of claim 13 wherein the electronic devices are surface acoustic wave devices.
Claim 16
Dependent Claim
125 words
A wafer level package comprising: a single substrate wafer and a plurality of individual electronic devices, wherein said electronic devices are supported by said substrate wafer at the wafer level; a cover wafer bonded against said substrate wafer over said electronic devices; a grid of bonding material patterned upon said substrate wafer in a manner separating each one of said electronic devices supported thereby from the remaining of said electronic devices supported thereby; wherein said bonding material and said cover wafer aid in forming a seal for substantially each cue of said electronic devices at the wafer level; a plurality of electrically conductive elements in said cover wafer, wherein said electrically conductive elements are in electrical communication with said electronic devices at the wafer level.
Claim 17
Dependent Claim
125 words
A wafer level package comprising: a single substrate wafer and a plurality of individual electronic devices, wherein said electronic devices are supported by said substrate wafer at the wafer level; a cover wafer bonded against said substrate wafer over said electronic devices; a grid of bonding material patterned upon said substrate wafer in a manner separating each one of said electronic devices supported thereby from the remaining of said electronic devices supported thereby; wherein said bonding material and said cover wafer aid in forming a seal for substantially each cue of said electronic devices at the wafer level; a plurality of electrically conductive elements in said cover wafer, wherein said electrically conductive elements are in electrical communication with said electronic devices at the wafer level.
Claim 18
Dependent Claim
23 words
The wafer level package of claim 15 wherein each of said substrate wafer and said cover wafer are at least one inch wide.
Claim 19
Dependent Claim
55 words
The wafer level package of claim 15 wherein the seal is a hermetic seal; and wherein the cover wafer comprises an electrically nonconductive material having thermal expansion characteristics similar to the thermal expansion characteristics of the substrate wafer; and wherein the plurality of electrically conductive elements in the cover wafer comprise hermetically sealed conductive vias.
Claim 20
Dependent Claim
16 words
The wafer level package of claim 17 wherein the electronic devices are surface acoustic wave devices.
Claim 21
Dependent Claim
34 words
The method of claim 1 further comprising a step prior to step (c) of forming a solder layer on an outer side of one of said wafers for subsequent use in solder attachment procedures.
Claim 22
Dependent Claim
55 words
The method of claim 9 further comprising a multiple layer grid, wherein said solder strips comprise at least one layer of said grid; and wherein said multiple layer grid additionally includes a barrier layer, wherein said barrier layer at least in part aids in maintaining the separation between the substrate wafer and the cover wafer.
Claim 23
Dependent Claim
16 words
The method of claim 1 wherein the steps (b)(i) and (b)(ii) both take place essentially concurrently.
Claim 24
Dependent Claim
16 words
The wafer level package of claim 15 wherein the electronic devices are surface acoustic wave devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-09-04 | 1999-03-06 | 1999-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-09-04 | 2003-03-06 | 2003-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-09-04 | 2007-03-06 | 2007-09-05 | $7700.00 | Window Closed / Lapsed |