Patent US5447877A successfully refreshed from Google Patents.
US5447877A
Expired / Lapsed
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Method of manufacturing nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1993-10-08
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Granted: 1995-09-05
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Expires: 2013-10-08
Abstract
Abstract A plurality of memory cells are formed on a semiconductor substrate. Each memory cell contains a first gate insulating film formed on the semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, a control gate formed on the second gate insulating film, and a source and a drain region formed in the semiconductor substrate on both sides of the floating gate, respectively. The source regions of the memory cells are connected with a plurality of common source lines. At least the surface of these source regions in the vicinity of the ends of the floating gate are made flush with the surface of the semiconductor substrate under the floating gate.
Inventors
- 👤 Hiroyuki Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:53
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
322 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said floating gate, said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming a thermal oxide film on the surface of the first structure; coating the element regions except for at least a common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said thermal oxide film on said source-region formation-scheduled area so as to expose the semiconductor substrate in said source-region formation-scheduled area; selectively growing a protective film on the surface of the semiconductor substrate exposed in said source-region formation-scheduled area, the etching rate of the protective film being lower than the etching rate of the field oxide film regions; etching away said protective film and said field oxide film regions on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; and implanting impurity ions into said common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner.
Claim 2
Dependent Claim
322 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said floating gate, said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming a thermal oxide film on the surface of the first structure; coating the element regions except for at least a common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said thermal oxide film on said source-region formation-scheduled area so as to expose the semiconductor substrate in said source-region formation-scheduled area; selectively growing a protective film on the surface of the semiconductor substrate exposed in said source-region formation-scheduled area, the etching rate of the protective film being lower than the etching rate of the field oxide film regions; etching away said protective film and said field oxide film regions on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; and implanting impurity ions into said common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner.
Claim 3
Dependent Claim
51 words
A method according to claim 1, wherein the step of etching away said thermal oxide film on said source region formation-scheduled area so as to expose the semiconductor substrate in the source region formation-scheduled area is carried out by first performing RIE and thereafter effecting chemical etching by using ammonium fluoride.
Claim 4
Dependent Claim
17 words
A method according to claim 1, wherein said protective film is made of either tungsten or molybdenum.
Claim 5
Dependent Claim
322 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming an insulating film on the entire first structure, the thickness of the insulating film formed on sidewalls of the first structure being substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least a common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film regions and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; implanting impurity ions into said common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner; completely removing said photoresist and said insulating film to form a second structure; and forming a thermal oxide film on the surface of the second structure.
Claim 6
Dependent Claim
322 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming an insulating film on the entire first structure, the thickness of the insulating film formed on sidewalls of the first structure being substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least a common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film regions and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; implanting impurity ions into said common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner; completely removing said photoresist and said insulating film to form a second structure; and forming a thermal oxide film on the surface of the second structure.
Claim 7
Dependent Claim
18 words
A method according to claim 4, wherein said insulating film is a SiO 2 film formed by CVD.
Claim 8
Dependent Claim
318 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said floating gate, said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming a thermal oxide film on the entire first structure; implanting impurity ions into a common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner; coating the element regions except for at least said common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source-regions; etching away said thermal oxide film formed on the entire first structure to expose the semiconductor substrate in said source-region formation-scheduled area; selectively growing a protective film on the surface of the semiconductor substrate exposed in said source-region formation-scheduled area, the etching rate of the protective film being lower than the etching rate of the field oxide film regions; and etching away said protective film and said field oxide film regions on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area.
Claim 9
Dependent Claim
318 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said floating gate, said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming a thermal oxide film on the entire first structure; implanting impurity ions into a common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner; coating the element regions except for at least said common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source-regions; etching away said thermal oxide film formed on the entire first structure to expose the semiconductor substrate in said source-region formation-scheduled area; selectively growing a protective film on the surface of the semiconductor substrate exposed in said source-region formation-scheduled area, the etching rate of the protective film being lower than the etching rate of the field oxide film regions; and etching away said protective film and said field oxide film regions on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area.
Claim 10
Dependent Claim
320 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film, at specified intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film and said element region; implanting impurity ions into a common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner, thus forming a first structure; forming an insulating film on the first structure, the thickness of the insulating film formed on sidewalls of the first structure being set substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least said common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; completely removing said photoresist and said insulating film to form a second structure; and forming a thermal oxide film on the surface of the second structure.
Claim 11
Dependent Claim
320 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film, at specified intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film and said element region; implanting impurity ions into a common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner, thus forming a first structure; forming an insulating film on the first structure, the thickness of the insulating film formed on sidewalls of the first structure being set substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least said common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; completely removing said photoresist and said insulating film to form a second structure; and forming a thermal oxide film on the surface of the second structure.
Claim 12
Dependent Claim
322 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming an insulating film on the first structure, the thickness of the insulating film formed on sidewalls of the first structure being substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least a common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film regions and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; implanting impurity ions into said common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner; completely removing said photoresist, thus forming a second structure; and forming an insulating film on the surface of the second structure after said photoresist is completely removed.
Claim 13
Dependent Claim
322 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film regions, at intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control gate formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film regions and said element regions, thus forming a first structure; forming an insulating film on the first structure, the thickness of the insulating film formed on sidewalls of the first structure being substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least a common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film regions and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; implanting impurity ions into said common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner; completely removing said photoresist, thus forming a second structure; and forming an insulating film on the surface of the second structure after said photoresist is completely removed.
Claim 14
Dependent Claim
320 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film, at specified intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film and said element region; implanting impurity ions into a common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner, thus forming a first structure; forming an insulating film on the first structure, the thickness of the insulating film formed on sidewalls of the first structure being set substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least said common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; completely removing said photoresist, thus forming a second structure; and forming an insulating film on the surface of the second structure after said photoresist is completely removed.
Claim 15
Dependent Claim
320 words
A manufacturing method of semiconductor memory devices, comprising the steps of: forming a plurality of field oxide films at intervals in stripes on the surface of a semiconductor substrate so as to arrange field oxide film regions and element regions one after another alternately on the surface of the semiconductor substrate; forming a plurality of striped multilayer gate structures in a direction substantially perpendicular to said field oxide film, at specified intervals above said semiconductor substrate, each multilayer gate structure having a first gate insulating film formed on said semiconductor substrate, a floating gate formed on the first gate insulating film, a second gate insulating film formed on the floating gate, and a control formed on the second gate insulating film, said first gate insulating film and said floating gate being formed on said element region, and said second gate insulating film and said control gate being formed on said field oxide film and said element region; implanting impurity ions into a common-source line formation-scheduled area in said semiconductor substrate, with said multilayer gate structure as a mask, so as to form common source lines containing source regions in said common-source line formation-scheduled area in a self-aligning manner, thus forming a first structure; forming an insulating film on the first structure, the thickness of the insulating film formed on sidewalls of the first structure being set substantially equal to the thickness of said field oxide film regions; coating the element regions except for at least said common-source line formation-scheduled area with a photoresist, said common-source line formation-scheduled area containing source regions; etching away said field oxide film and said insulating film on said common-source line formation-scheduled area so as to expose the surface of the semiconductor substrate in said common-source line formation-scheduled area; completely removing said photoresist, thus forming a second structure; and forming an insulating film on the surface of the second structure after said photoresist is completely removed.
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