US5246874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making fast access AMG EPROM
Assignee: National Semiconductor Corp
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Filing: 1992-06-02
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Granted: 1993-09-21
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Expires: 2012-06-02
Abstract
Abstract A fast access EPROM array formed in a silicon substrate of P-type conductivity comprises a layer of gate oxide formed on the silicon substrate. A first layer of polysilicon is formed on the gate oxide. A layer of oxide/nitride/oxide composite is formed on the first polysilicon layer. The ONO and underlying Poly1 define a plurality of parallel strips. N-type dopant introduced into the silicon substrate between the ONO/Poly1 strips define buried N+ bit lines. Alternate buried N+ bit lines to define drain lines that alternate with buried N+ source lines. Each of the drain lines is contacted only once for a plurality of EPROM cells sharing that drain line such that the EPROM array is subdivided into a plurality of segments. The source lines are uncontacted. A plurality of Poly2 wordlines are formed perpendicular to the ONO/Poly1 strips such that an intersection of the Poly2 word lines and the Poly1 floating gate define the location of a cross-point EPROm cell of the array. Each segment of the array include first and second Poly2 select lines the intersection of which with the Poly1 defines first and second select transistors such that each buried N+ source line is electrically connectable to one of its adjacent drain lines via the first select transistor and to the other adjacent drain line via the second select transistor. Finally, each segment also includes a segment select line that defines the gate of a segment select transistor associated with each drain line.
Inventors
- 👤 Albert Bergemont
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 07:02
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/40; H10B41/42; H10B41/43; H10B41/44
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
405 words
A method of fabricating a fast access EPROM array in a silicon substrate of P-type conductivity, the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a layer of first conductive material on the first insulating material; (c) forming a layer of second insulating material on the layer of first conductive material; (d) etching selected portions of the layer of second insulating material and underlying first conductive material to form a plurality of spaced-apart parallel strips of second insulating material and underlying first conductive material; (e) introducing N-type dopant into the silicon substrate regions between the parallel strips of second insulating material and underlying first conductive material to formed space-apart buried N+ bit lines, alternate buried N+ bit lines forming drain lines that alternate with buried N+ source lines, each of the drain lines having only one electrical contact for a plurality of EPROM cells sharing said drain line such that the EPROM array is subdivided into a plurality of segments, the source lines being uncontacted; (f) forming a plurality of spaced-apart parallel word lines of second conductive material, said word lines formed perpendicular to the strips of second insulating material and underlying first conductive material and such that the second conductive material is separated from the first conductive material by the second insulating material whereby the intersection of the first and second conductive material defines the location of a cross-point EPROM cell of the array; (g) forming first and second spaced-apart parallel select lines of second conductive material in each segment of the array said select lines formed perpendicular to the strips of second insulating material and underlying first conductive material and such that the second conductive material is separated from the first conductive material by the second insulating material whereby the intersection of the first and second select lines with the first conductive material defines the location of first and second select transistors such that each buried N+ source line is electrically connectable to one of its adjacent drain lines via the first select transistor having its gate provided by the first select line and to the other adjacent drain line via a second select transistor having its gate provided by the second select line; (h) forming first and second segment select lines in each segment of the array, said segment select lines defining the gate of a segment select transistor associated with each drain line.
Claim 2
Independent Claim
405 words
A method of fabricating a fast access EPROM array in a silicon substrate of P-type conductivity, the method comprising: (a) forming a layer of first insulating material on the silicon substrate; (b) forming a layer of first conductive material on the first insulating material; (c) forming a layer of second insulating material on the layer of first conductive material; (d) etching selected portions of the layer of second insulating material and underlying first conductive material to form a plurality of spaced-apart parallel strips of second insulating material and underlying first conductive material; (e) introducing N-type dopant into the silicon substrate regions between the parallel strips of second insulating material and underlying first conductive material to formed space-apart buried N+ bit lines, alternate buried N+ bit lines forming drain lines that alternate with buried N+ source lines, each of the drain lines having only one electrical contact for a plurality of EPROM cells sharing said drain line such that the EPROM array is subdivided into a plurality of segments, the source lines being uncontacted; (f) forming a plurality of spaced-apart parallel word lines of second conductive material, said word lines formed perpendicular to the strips of second insulating material and underlying first conductive material and such that the second conductive material is separated from the first conductive material by the second insulating material whereby the intersection of the first and second conductive material defines the location of a cross-point EPROM cell of the array; (g) forming first and second spaced-apart parallel select lines of second conductive material in each segment of the array said select lines formed perpendicular to the strips of second insulating material and underlying first conductive material and such that the second conductive material is separated from the first conductive material by the second insulating material whereby the intersection of the first and second select lines with the first conductive material defines the location of first and second select transistors such that each buried N+ source line is electrically connectable to one of its adjacent drain lines via the first select transistor having its gate provided by the first select line and to the other adjacent drain line via a second select transistor having its gate provided by the second select line; (h) forming first and second segment select lines in each segment of the array, said segment select lines defining the gate of a segment select transistor associated with each drain line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-09-20 | 1997-03-22 | 1997-09-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-09-20 | 2001-03-22 | 2001-09-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-09-20 | 2005-03-22 | 2005-09-21 | $7700.00 | Window Closed / Lapsed |