Flexible graphics interface device switch selectable big and little endian modes, systems and methods

Claim 2

A color palette comprising: a plurality of first inputs for receiving multiple bits of color codes in a data format selected from the group consisting of the big-endian and little-endian data formats; a plurality of second inputs for receiving multiple-bit color data words in said selected data format; a plurality of third inputs for receiving multiple-bit write address words in said selected data format; a selector coupled to said first inputs for receiving at least some of said multiple bits of color code and outputting at least one recall address in response; a memory coupled to said selector and having a plurality of data storage locations, each said location having an associated said recall address and an associated said write address, said memory operable to output a said color data word written into a said location upon receipt of a said associated recall address from said selector; an interpreter circuit coupled to said plurality of third inputs for selectively interpreting said selected format of a said write address received at said third inputs into an other one of said big-endian and little-endian formats; and write circuitry coupled to said interpreter circuit and said second inputs for writing a said color data word received at said second inputs to a said location in said memory associated with said write address received from said interpreter circuit.

Claim 3

The color palette of claim 1, wherein said plurality of third inputs comprise j sequentially ordered inputs and said interpreter circuit comprises: an array of j sequentially ordered first AND gates, each said first AND gate having first and second input ports and an output port, said first input port of an m th one of said first AND gates coupled to an m th one of said third input terminals, said input ports of said first AND gates coupled to a first control signal; an array of j sequentially ordered second AND gates, each said second AND gate having first and second input ports and an output port, said first input port of an n th one of said second AND gates coupled to a (j-n+1) th one of said third input terminals, said second input ports of said second AND gates coupled to a second control signal; an array of j sequentially ordered OR gates each having first and second input ports and an output port, said first input of an m th one of said OR gates coupled to said output of said m th one of said first AND gates and second input port of n th one of said OR gates coupled to said output of said n th one of said second AND gates; and wherein, j is a constant, m is a variable between 1 and j, and n is a variable between 1 and j.

Claim 4

The color palette of claim 2, wherein j is a power of 2.

Claim 5

The color palette of claim 2, wherein j is equal to 8.

Claim 6

The color palette of claim 2, wherein said second control signal is the complement of said first control signal.

Claim 7

The color palette of claim 2, wherein said memory comprises a dual-port random access memory having a first address port coupled to said selector for receiving a said recall address, a second address port coupled to said write circuitry for receiving a said write address and a data port coupled to said write circuitry for receiving said color data word.

Claim 8

The color palette of claim 6, wherein said write circuitry comprises: an address register having j inputs coupled to said outputs of said j sequentially ordered OR gates and a plurality of outputs coupled to said second address port of said memory; a holding register having a plurality of inputs coupled to said plurality of second input ports and a plurality of outputs coupled to said data input port of said memory.

Claim 9

The color palette of claim 1 and further comprising bypass circuitry including an output multiplexer coupled to said memory and selected ones of said first inputs and operable to select for output between color data words received from said memory and selected ones of said bits of color code received at said selected ones of said first inputs.

Claim 10

The color palette of claim 8, wherein said bypass circuitry further comprises a second interpreter circuit coupled to said selected ones of said first inputs and said output multiplexer, said second interpreter circuit operable to selectively interpret said selected ones of said bits of color code received at said selected ones of said first inputs to said other one of said big-endian and little-endian data formats.

Claim 11

The color palette of claim 9, wherein said selected ones of said first inputs comprise k inputs and said second interpreter circuit comprises: an array of k sequentially ordered first AND gates, each said first AND gate having first and second input ports and an output port, said first input port of a p th one of said first AND gates coupled to a p th one of said selected first input terminals, said second input ports of said first AND gates coupled to said first control signal; an array of k sequentially ordered second AND gates, each said second AND gate having first and second input ports and an output port, said first input port of a q th one of said second AND gates coupled to a (k-q+1) th one of said selected first input terminals, said second input ports of said second AND gates coupled to said second control signal; an array of k sequentially ordered OR gates each having first and second input ports and an output port, said first input of a p th one of said OR gates coupled to said output of said p th one of said first AND gates and said second input port of a q th one of said OR gates coupled to said output of said q th one of said second AND gates; wherein k is a constant, p is a variable between 1 and k, and q is a variable between 1 and k.

Claim 12

The color palette of claim 10, wherein k is equal to 24.

Claim 13

The color palette of claim 11, wherein said plurality of first inputs comprise 1 inputs and wherein 1 is a power of 2.

Claim 14

The color palette of claim 12, wherein l=32 and k=24.

Claim 15

The color palette of claim 13, wherein said plurality of third inputs comprise r inputs and wherein r is a power of 2.

Claim 16

The color palette of claim 14, wherein r=8.

Claim 17

A color palette comprising: a plurality of inputs for receiving multiple bits of color code and multiple bits of true-color data in a data format selected from the group consisting of the big-endian and little-endian data formats; a selector coupled to said inputs for receiving at least some of said multiple bits of color code and outputting at least one recall address in response; a memory coupled to said selector and having a plurality of data storage locations, each said location having an associated said recall address and an associated multiple-bit write address, said memory operable to output a color data word written into a said location upon receipt of a said associated recall address from said selector; bypass circuitry comprising: an interpreter circuit coupled to selected ones of said first inputs and said output multiplexer, said conversion circuit operable to selectively convert bits of true-color data received at said selected ones of said first inputs to an other one of said big-endian and little-endian data formats; an output multiplexer coupled to said memory and said interpreter circuit and operable to select for output between said bits of color codes received at said selected ones of said inputs and true-color data output from said memory in response to a said recall address comprising bits of said multiple-bit color codes received at other ones of said inputs.

Claim 18

A color palette comprising: a plurality of inputs for receiving multiple bits of color code and multiple bits of true-color data in a data format selected from the group consisting of the big-endian and little-endian data formats; a selector coupled to said inputs for receiving at least some of said multiple bits of color code and outputting at least one recall address in response; a memory coupled to said selector and having a plurality of data storage locations, each said location having an associated said recall address and an associated multiple-bit write address, said memory operable to output a color data word written into a said location upon receipt of a said associated recall address from said selector; bypass circuitry comprising: an interpreter circuit coupled to selected ones of said first inputs and said output multiplexer, said conversion circuit operable to selectively convert bits of true-color data received at said selected ones of said first inputs to an other one of said big-endian and little-endian data formats; an output multiplexer coupled to said memory and said interpreter circuit and operable to select for output between said bits of color codes received at said selected ones of said inputs and true-color data output from said memory in response to a said recall address comprising bits of said multiple-bit color codes received at other ones of said inputs.

Claim 19

The color palette of claim 16, wherein said selected ones of said inputs comprise k inputs and said interpreter circuit comprises: an array of k sequentially ordered first AND gates, each said first AND gate having first and second input ports and an output port, said first input port of a p th one of said first AND gates coupled to a p th one of said selected input terminals, said second input ports of said first AND gates coupled to said first control signal; an array of k sequentially ordered second AND gates, each said second AND gate having first and second input ports and an output port, said first input port of a q th one of said second AND gates coupled to a (k-q+1) th one of said selected first input terminals, said second input ports of said second AND gates coupled to said second control signal; an array of k sequentially ordered OR gates each having first and second input ports and an output port, said first input of a p th one of said OR gates coupled to said output of said p th one of said first AND gates and said second input port of a q th one of said OR gates coupled to said output of said q th one of said second AND gates; wherein k is a constant, p is a variable between 1 and k, and q is a variable between 1 and k.

Claim 20

The color palette of claim 16 and further comprising: a plurality of second inputs for receiving multiple-bit color data words in said selected data format; a plurality of third inputs for receiving said multiple-bit write address words in said selected data format; a second interpreter circuit coupled to said plurality of third inputs for selectively interpreting said selected format of a said write address word received at said third inputs into an other one of said big-endian and little-endian formats; and write circuitry coupled to said conversion circuit and said second inputs for writing a said color word received at said second inputs to a said location in said memory associated with a said write address received from said conversion circuit.

Claim 21

The color palette of claim 18, wherein said plurality of third inputs comprise j sequentially ordered inputs and said second interpreter circuit comprises: an array of j sequentially ordered first AND gates, each said first AND gate having first and second input ports and an output port, said first input port of an m th one of said first AND gates coupled to an m th one of said third input terminals, said input ports of said first AND gates coupled to a first control signal; an array of j sequentially ordered second AND gates, each said second AND gate having first and second input ports and an output port, said first input port of an n th one of said second AND gates couples to a (j-n+1 th ) one of said input terminals, said second input ports of said second AND gates coupled to a second control signal; an array of j sequentially ordered OR gates each having first and second input ports and an output port, said first input of an m th one of said OR gates coupled to said output of said m th one of said first AND gates and second input port of n th one of said OR gates coupled to said output of said n th one of said second AND gates; and wherein, j is a constant, m is a variable between 1 and j, and n is a variable between 1 and j.

Claim 22

A graphics processor system comprising: a graphics processor controlling said system and operating in a data format selected from the big-endian and little-endian formats; a video memory coupled to said processor for storing a plurality of multiple-bit color codes in said selected format and defining a video image to be displayed as a plurality of pixels; a color palette comprising: a plurality of first inputs coupled to said video memory for receiving said color codes from said video memory under the control of said processor; a plurality of second inputs coupled to said processor for receiving multiple-bit color data words in said selected data format and defining colors of said pixels; a plurality of third inputs coupled to said processor for receiving multiple-bit write address words in said selected data format; a selector coupled to said first inputs for receiving at least some of said bits of said multiple-bits of color code and outputting at least one recall address in response; a memory coupled to said selector and having a plurality of data storage locations, each said location having an associated said recall address and an associated write address word, said memory operable to output a said color data word written into said location upon receipt of a said associated recall address from said selector; bypass circuitry comprising: an interpreter circuit coupled to selected ones of said first inputs, said interpreter circuit operable to selectively interpret said bits of color codes received at said selected ones of said first inputs to an other one of said big-endian and little-endian data formats; an output multiplexer coupled to said memory and said interpreter circuit and operable to select data for output between said bits of color codes received at said selected ones of said inputs and color data words output from said memory in response to a said recall address comprising bits of said multiple-bit color codes at other of said inputs; a second interpreter circuit coupled to said plurality of third inputs for receiving multiple-bit write address words in said selected data format, said second interpreter circuit operable to selectively interpret said write address words received a said third inputs to an other one of said big-endian and little-endian data formats; write circuitry coupled to said memory, said second interpreter circuit and said second inputs for writing a color data word received at said second inputs to a said location in said memory associated with said write address word received from said second interpreter circuit; digital-to-analog converter circuitry coupled to said output multiplexer for converting said data selected for output into analog form; and a display coupled to said digital-to-analog converter circuitry for displaying selected images as a plurality of pixels.

Claim 23

A graphics processor system comprising: a graphics processor controlling said system and operating in a data format selected from the big-endian and little-endian formats; a video memory coupled to said processor for storing a plurality of multiple-bit color codes in said selected format and defining a video image to be displayed as a plurality of pixels; a color palette comprising: a plurality of first inputs coupled to said video memory for receiving said color codes from said video memory under the control of said processor; a plurality of second inputs coupled to said processor for receiving multiple-bit color data words in said selected data format and defining colors of said pixels; a plurality of third inputs coupled to said processor for receiving multiple-bit write address words in said selected data format; a selector coupled to said first inputs for receiving at least some of said bits of said multiple-bits of color code and outputting at least one recall address in response; a memory coupled to said selector and having a plurality of data storage locations, each said location having an associated said recall address and an associated write address word, said memory operable to output a said color data word written into said location upon receipt of a said associated recall address from said selector; bypass circuitry comprising: an interpreter circuit coupled to selected ones of said first inputs, said interpreter circuit operable to selectively interpret said bits of color codes received at said selected ones of said first inputs to an other one of said big-endian and little-endian data formats; an output multiplexer coupled to said memory and said interpreter circuit and operable to select data for output between said bits of color codes received at said selected ones of said inputs and color data words output from said memory in response to a said recall address comprising bits of said multiple-bit color codes at other of said inputs; a second interpreter circuit coupled to said plurality of third inputs for receiving multiple-bit write address words in said selected data format, said second interpreter circuit operable to selectively interpret said write address words received a said third inputs to an other one of said big-endian and little-endian data formats; write circuitry coupled to said memory, said second interpreter circuit and said second inputs for writing a color data word received at said second inputs to a said location in said memory associated with said write address word received from said second interpreter circuit; digital-to-analog converter circuitry coupled to said output multiplexer for converting said data selected for output into analog form; and a display coupled to said digital-to-analog converter circuitry for displaying selected images as a plurality of pixels.

Claim 24

The color palette of claim 20, wherein said plurality of third inputs comprise j sequentially ordered inputs and said second interpreter circuit comprises: an array of j sequentially ordered first AND gates, each said first AND gate having first and second input ports and an output port, said first input port of an m th one of said first AND gates coupled to an m th one of said third input terminals, said input ports of said first AND gates coupled to a first control signal; an array of j sequentially ordered second AND gates, each said second AND gate having first and second input ports and an output port, said first input port of an n th one of said second AND gates coupled to a (j-n+1) th one of said input terminals, said second input ports of said second AND gates coupled to a second control signal; an array of j sequentially OR gates each having first and second input ports and an output port, said first input of an m th one of said OR gates coupled to said output of said m th one of said first AND gates and second input port of n th one of said OR gates coupled to said output of said n th one of said second AND gates, and wherein, j is a constant, m is a variable between 1 and j, and n is a variable between 1 and j.

Claim 25

A color palette comprising: a plurality of inputs for receiving multiple bits of color codes in a data format selected from the group consisting of the big-endian and little-endian data formats; an interpreter circuit coupled to said plurality of inputs for selectively mirroring said bits of color codes; a selector coupled to said interpreter circuit for receiving said multiple bits of color codes and outputting at least one recall address in response, said selector further operable to selectively mirror bits comprising each said recall address; and a memory coupled to said selector and having a plurality of data storage locations, each said location having an associated said recall address, said memory operable to output a color data word written into a said location upon receipt of an associated said recall address from said selector.

Claim 26

A color palette comprising: a plurality of inputs for receiving multiple bits of color codes in a data format selected from the group consisting of the big-endian and little-endian data formats; an interpreter circuit coupled to said plurality of inputs for selectively mirroring said bits of color codes; a selector coupled to said interpreter circuit for receiving said multiple bits of color codes and outputting at least one recall address in response, said selector further operable to selectively mirror bits comprising each said recall address; and a memory coupled to said selector and having a plurality of data storage locations, each said location having an associated said recall address, said memory operable to output a color data word written into a said location upon receipt of an associated said recall address from said selector.

Claim 27

The color palette of claim 22 wherein said selector is operable to mirror said bits comprising each said recall address following mirroring of said bits of color codes by said interpreter circuit.

Claim 28

The color palette of claim 22 wherein said selector circuit is operable to selectively mirror said bits comprising said recall address as a function of the number of said bits comprising said recall address.

Claim 29

The color palette of claim 22 wherein said plurality of inputs comprise k inputs and said interpreter circuit comprises: an array of k sequentially ordered first AND gates, each said first AND gate having first and second input ports and an output port, said first input port of a p th one of said first AND gates coupled to a p th one of said selected input terminals, said input ports of said first AND gates coupled to said first control signals; an array of k sequentially ordered second AND gates, each said second AND gate having first and second input ports and an output port, said first input port of a q th one of said second AND gates coupled to a (k-q+1) th one of said selected first input terminals, said second input ports of said second AND gates coupled to said second control signal; an array of k sequentially ordered OR gates each having first and second input ports and an output port, said first input of a p th one of said OR gates coupled to said output of said p th one of said first AND gates and said second input port of a q th one of said OR gates coupled to said output of said q th one of said second AND gates; wherein k is a constant, p is a variable between 1 and k, and q is a variable between 1 and k.