Color graphics control system

Claim 2

A color graphics control system for generating electrical signal values for respective color inputs to a raster scan color display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for a scanning sequence, said control system comprising: a RAM having a memory array having a plurality of addressable locations each storing digital color value data; a digital to analog converter circuit coupled to receive digital color value data from said RAM, said converter circuit being responsive to each color value data to generate a corresponding combination of analog electrical signals representing respectively red, blue and green color values for each pixel in a raster scan display; a timing circuit for indicating a pixel frequency corresponding to that of the raster scan and for generating timing control signals for synchronizing the generation of said analog signals at said pixel frequency; said RAM including receiving means and decoding circuitry coupled to receive a succession of pixel values from the pixel memory device at the pixel frequency, said receiving means and decoding circuitry being responsively coupled to said timing circuit for causing a multistage accessing operation including addressing and reading from a corresponding location of said memory array a digital color value for supplying to said digital to analog converter circuit; and an interface coupled to said RAM for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital color values into one or more locations in said memory array; said timing circuit being coupled to said receiving means and decoding circuitry so that a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a memory array location and reading the digital color value for each pixel value.

Claim 3

A color graphics control system according to claim 1 wherein said timing circuit is coupled to control said decoding circuitry so that each accessing operation extends over two successive pixel periods.

Claim 4

A color graphics control system according to claim 1 wherein each location of said memory array stores a multi-bit data value having bit groups representing red, blue and green color values, and said digital to analog converter circuit comprises three digital to analog converters coupled to receive separately a respective bit group so that they operate in parallel to provide simultaneously red, blue and green analog signals.

Claim 5

A color graphics control system according to claim 1 in which said interface includes temporary store means coupled for receiving data from a microprocessor or other controller for use in writing into said RAM and access means for controlling the loading of data into said temporary store means, said access means being operable independently of pixel clock timing to permit asynchronous loading of data into said interface.

Claim 6

A color graphics control system according to claim 4 in which said temporary store means includes means for holding a RAM address and means for holding a digital color value to be written into said RAM address.

Claim 7

A color graphics control system according to claim 5 further including means for incrementing the RAM address in said temporary store means after each writing operation.

Claim 8

A color graphics control system according to claim 4 in which said timing circuit includes a pixel clock providing signals at the pixel frequency and said interface includes synchronizing means arranged to receive timing signals from said timing circuit so that a writing operation from the interface into said RAM is synchronized with the pixel clock.

Claim 9

A color graphics control system according to claim 7 in which said writing operation is a multi-stage operation having a cycle time of more than one pixel period, each stage of said multi-stage operation being controlled by said timing circuit so that a pipeline effect is achieved in writing in synchronism with the pixel clock over more than one period of the pixel frequency.

Claim 10

A color graphics control system according to claim 3 wherein each of said digital to analog converters includes a plurality of parallel current sources coupled to a common reference voltage, switch means responsive to said digital color value to control the number of current sources switched to form an analog output, and means for stabilizing the current derived from each current source so that it is independent of the number of parallel current sources that are switched on or off and thereby reduce non-linearity of the digital to analog conversion.

Claim 11

A color graphics control system according to claim 9 in which each current source comprises a first transistor with said reference voltage forming a gate voltage for the transistor, the means for stabilizing comprising differential amplifier circuit means responsive to current fluctuations through said first transistor and arranged to provide a compensating voltage to the gate of a further transistor in series with said first transistor.

Claim 12

A color graphics control system according to claim 3 in which each digital to analog converter includes a plurality of current sources together with switch means responsive to said digital color value to control the number of current sources operable in response to a digital color value, said current sources forming a plurality of groups of different numbers of current sources, all the current sources in each group being coupled to be switched on or off together by a single binary coded signal.

Claim 13

A color graphics control system according to claim 1 wherein said digital to analog converter circuit includes means for receiving a said color value data, said color value data comprising a multi-bit binary encoded signal representing a digital color value for conversion to an analog signal, said digital to analog converter circuit further comprising a plurality of selectively operable current sources with switch means for operating a selected number of current sources corresponding to the value of said multi-bit signal, said current sources being grouped into a plurality of groups wherein all current sources in a group are switched together, the groups having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group having a number of current sources representing less than the bit of maximum significance in said multi-bit signal, decoding means being provided for decoding said multi-bit signal and providing a number of switch actuating signals greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group of current sources, thereby reducing the magnitude of any group of current sources necessary to be switched at any time.

Claim 14

A color graphics control system according to claim 12 wherein the groups of current sources include a first group including progressively increasing numbers of current sources each corresponding to the numerical value of successive bit locations in said multi-bit signal and a second group at least one of which includes the maximum number of current sources to be switched as a single group, the second group being combined to represent the bit of maximum significance in the multi-bit signal.

Claim 15

A color graphics control system according to claim 1 wherein said RAM, interface and digital to analog converter circuit are formed on a single integrated circuit device.

Claim 16

A color graphics control system according to claim 14 wherein each addressable location in said memory array is arranged to store an 18-bit word, said word having three groups of six bits representing respectively the color values for red, blue and green.

Claim 17

A color graphics control system according to claim 15 wherein said RAM provides 256 addressable word locations.

Claim 18

A color graphics control system for generating electrical signal values for respective color inputs to a raster scan color display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for scanning sequence, said control system comprising: a RAM having a plurality of addressable locations each storing a digital color value, digital to analog converters respectively for red, blue and green signals, each arranged to receive a multi-bit digital color value from said RAM and in response to each color value to generate a corresponding analog electrical signal for each pixel in a raster scan display, each said digital to analog converter including means for receiving a multi-bit binary encoded signal and a plurality of selectively operable current sources with switch means for operating a selected number of current sources corresponding to the value of said multi-bit signal, said current sources being grouped into a plurality of groups wherein all current sources in a group are switched together, the groups having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group having a number of current sources representing less than the bit of maximum significance in said multi-bit signal, decoding means being provided for decoding said multi-bit signal and providing a number of switch actuating signals greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group of current sources, timing means for indicating a pixel frequency corresponding to that of the raster scan and generating timing control signals for synchronizing the generation of said analog signals at said pixel frequency, RAM accessing means for receiving a succession of pixel values from said pixel memory device at the pixel frequency and in response to each pixel value effecting a multi-stage accessing operation including addressing an corresponding location of the RAM and reading from the location a digital color value for supplying to said digital to analog converters, and an interface coupled to said RAM and arranged for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital color values into one or more locations in said RAM, said timing means being coupled to control each stage of RAM accessing wherein a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a RAM location and reading the digital color value for each pixel value.

Claim 19

A color graphics control system for generating electrical signal values for respective color inputs to a raster scan color display unit in response to a succession of pixel values derived from a pixel memory device storing pixel values for scanning sequence, said control system comprising: a RAM having a plurality of addressable locations each storing a digital color value, digital to analog converters respectively for red, blue and green signals, each arranged to receive a multi-bit digital color value from said RAM and in response to each color value to generate a corresponding analog electrical signal for each pixel in a raster scan display, each said digital to analog converter including means for receiving a multi-bit binary encoded signal and a plurality of selectively operable current sources with switch means for operating a selected number of current sources corresponding to the value of said multi-bit signal, said current sources being grouped into a plurality of groups wherein all current sources in a group are switched together, the groups having numbers of current sources corresponding to bits of different significance in said multi-bit signal with the largest group having a number of current sources representing less than the bit of maximum significance in said multi-bit signal, decoding means being provided for decoding said multi-bit signal and providing a number of switch actuating signals greater than the number of bits in said multi-bit signal, each switch actuating signal being provided for a respective group of current sources, timing means for indicating a pixel frequency corresponding to that of the raster scan and generating timing control signals for synchronizing the generation of said analog signals at said pixel frequency, RAM accessing means for receiving a succession of pixel values from said pixel memory device at the pixel frequency and in response to each pixel value effecting a multi-stage accessing operation including addressing an corresponding location of the RAM and reading from the location a digital color value for supplying to said digital to analog converters, and an interface coupled to said RAM and arranged for connection to a microprocessor or other controller to permit the microprocessor or other controller to write different digital color values into one or more locations in said RAM, said timing means being coupled to control each stage of RAM accessing wherein a pipeline effect is achieved with a cycle time of more than one pixel period for addressing a RAM location and reading the digital color value for each pixel value.

Claim 20

A color graphics control method for generating electrical signals for respective color inputs to a color display comprising the steps of: storing digital color value data in a memory circuit; receiving a sequence of pixel values for a scanning sequence; in response to said sequence of pixel values, accessing data in the memory circuit by addressing said memory circuit and reading therefrom respective color value data for each said pixel value, said accessing occurring in multiple stages; providing timing signals from a pixel clock; converting said color value data which have been read from said memory circuit into analog signals representing red, blue and green color values; and controlling said addressing, reading and converting in accordance with said timing signals to pipeline said operation so that a digital color value for each pixel value is obtained at the pixel clock frequency even though the cycle time of said accessing is more than one pixel period.

Claim 21

A color graphics control method for generating electrical signals for respective color inputs to a color display comprising the steps of: storing digital color value data in a memory circuit; receiving a sequence of pixel values for a scanning sequence; in response to said sequence of pixel values, accessing data in the memory circuit by addressing said memory circuit and reading therefrom respective color value data for each said pixel value, said accessing occurring in multiple stages; providing timing signals from a pixel clock; converting said color value data which have been read from said memory circuit into analog signals representing red, blue and green color values; and controlling said addressing, reading and converting in accordance with said timing signals to pipeline said operation so that a digital color value for each pixel value is obtained at the pixel clock frequency even though the cycle time of said accessing is more than one pixel period.

Claim 22

A color graphics control method according to claim 18 further comprising storing digital color value data in a RAM memory circuit, writing different digital color values into one or more locations in the RAM, said writing comprising loading data from a controller into a temporary store in an operation independent of pixel clock timing, and subsequently transferring data from the temporary store to the RAM in a transfer operation synchronized with pixel clock timing.

Claim 23

A color graphics control method according to claim 18 wherein color value data is converted into analog signals representing red, blue and green color values by generating a multi-bit binary encoded signal representing a digital color value for conversion to an analog signal, decoding said multi-bit signal to provide a number of switch actuating signals greater than the number of bits in said multi-bit signal, and using each of said switch actuating signals to switch simultaneously respective groups of current sources, the groups of current sources having number of current sources corresponding to bits of different significance in said multi-bit signal with the largest group providing a current representing less than the bit of maximum significance in said multi-bit signal.

Claim 24

A color graphics control method according to claim 19 wherein color value data is converted into analog signals representing red, blue and green color values by generating a multi-bit binary encoded signal representing a digital color value for conversion to an analog signal, decoding said multi-bit signal to provide a number of switch actuating signals greater than the number of bits in said multi-bit signal, and using each of said switch actuating signals to switch simultaneously respective groups of current sources, the groups of current sources having number of current sources corresponding to bits of different significance in said multi-bit signal with the largest group providing a current representing less than the bit of maximum significance in said multi-bit signal.