Phase locked loop for synchronizing with carrier wave

Claim 2

A phase locked loop circuit for synchronizing with carrier wave comprising: a fixed oscillator for generating a clock signal including reference clock pulses; a variable divider for dividing the clock signal and generating a first reference signal and a second reference signal whose frequency is same as the frequency of the first reference signal and whose phase is shifted by 90 degrees with respect to the phase of the first reference signal, said variable divider varying the frequencies of the first reference signal and the second reference signal in accordance with a control signal; a first multiplier for multiplying an input signal by the first reference signal; an exclusive OR circuit for operating an exclusive OR of the input signal and an output signal of said first multiplier; a phase comparator for receiving the clock signal, the first reference signal, the second reference signal and the output signal of said exclusive OR circuit, and detecting a value and a direction of a phase difference between the input signal and the first reference signal to produce phase comparison signal including a series of clock pulses whose number corresponding to the value of the phase difference and indicative of the direction of the phase difference; and a loop filter for producing the control signal on the basis of the phase comparison signal.

Claim 3

A phase locked loop circuit according to claim 1, further comprising a second multiplier for multiplying the input signal by the second reference signal.

Claim 4

A phase locked loop circuit according to claim 1, wherein said phase comparison signal comprises a positive-direction phase difference signal indicating that the phase of the input signal is preceding the phase of the first reference signal and a negative-direction phase comparison signal indicating that the phase of the input signal is lagged behind the phase of the first reference signal.

Claim 5

A phase locked loop circuit according to claim 2, wherein said phase comparison signal comprises a positive-direction phase difference signal indicating that the phase of the input signal is preceding the phase of the first reference signal and a negative-direction phase comparison signal indicating that the phase of the input signal is lagged behind the phase of the first reference signal.

Claim 6

A phase locked loop circuit according to claim 3, wherein either of the positive-direction phase comparison signal and the negative-direction phase difference signal includes the series of clock pulses.

Claim 7

A phase locked loop circuit according to claim 4, wherein either of the positive-direction phase comparison signal and the negative-direction phase difference signal includes the series of clock pulses.

Claim 8

A phase locked loop circuit according to claim 1, wherein said phase comparison signal comprises the series of clock pulses at every half period of the input signal.

Claim 9

A phase locked loop circuit according to claim 2, wherein said phase comparison signal comprises the series of clock pulses at every half period of the input signal.

Claim 10

A phase locked loop circuit according to claim 1, wherein said variable divider comprising said fixed oscillator for generating reference clock pulses, and said clock pulses in the phase comparison signal are synchronized with the reference clock pulses generated by the fixed oscillator.

Claim 11

A phase locked loop circuit according to claim 2, wherein said variable divider comprising said fixed oscillator for generating reference clock pulses, and said clock pulses in the phase comparison signal are synchronized with the reference clock pulses Generated by the fixed oscillator.

Claim 12

A phase locked loop circuit for synchronizing with carrier wave comprising: a fixed oscillator for generating a clock signal including reference clock pulses; a variable divider for dividing the clock signal and generating a first reference signal and a second reference signal whose frequency is the same as the frequency of the first reference signal and whose phase is shifted by 90 degrees with respect to the phase of the first reference signal, said variable divider varying the frequencies of the first reference signal and the second reference signal in accordance with a control signal, the frequency of the first and second reference signal being lower than the frequency of the clock signal; a first multiplier for multiplying an input signal by the first reference signal; an exclusive OR circuit for operating an exclusive OR of the input signal and an output signal of said first multiplier; a phase comparator for receiving the clock signal, the first reference signal, the second reference signal and the output signal of said exclusive OR circuit, and detecting a value and a direction of a phase differences between the input signal and the first reference signal to produce a phase comparison signal including a series of clock pulses whose number corresponding to the value of the phase difference and indicative of the direction of the phase difference, the frequency of the series of clock pulses being identical to the frequency of the reference clock pulses; and a loop filter for producing the control signal on the basis of the phase comparison signal.

Claim 13

A phase locked loop circuit for synchronizing with carrier wave comprising: a fixed oscillator for generating a clock signal including reference clock pulses; a variable divider for dividing the clock signal and generating a first reference signal and a second reference signal whose frequency is the same as the frequency of the first reference signal and whose phase is shifted by 90 degrees with respect to the phase of the first reference signal, said variable divider varying the frequencies of the first reference signal and the second reference signal in accordance with a control signal, the frequency of the first and second reference signal being lower than the frequency of the clock signal; a first multiplier for multiplying an input signal by the first reference signal; an exclusive OR circuit for operating an exclusive OR of the input signal and an output signal of said first multiplier; a phase comparator for receiving the clock signal, the first reference signal, the second reference signal and the output signal of said exclusive OR circuit, and detecting a value and a direction of a phase differences between the input signal and the first reference signal to produce a phase comparison signal including a series of clock pulses whose number corresponding to the value of the phase difference and indicative of the direction of the phase difference, the frequency of the series of clock pulses being identical to the frequency of the reference clock pulses; and a loop filter for producing the control signal on the basis of the phase comparison signal.

Claim 14

A phase locked loop according to claim 11, wherein said phase comparator comprises means for producing a phase difference signal indicating a value and direction of the phase difference, and means for producing the phase comparison signal from the phase difference signal and the clock signal.

Claim 15

A phase locked loop according to claim 12, wherein said phase comparison signal producing means comprises an AND circuit for operating an AND of the phase difference signal and the clock signal.