ROM with Bi-CMOS gate arrays

Claim 2

A semiconductor integrated circuit of the gate array type, comprising: a plurality of basic cells arranged in a matrix, each of the basic cells comprising a plurality of MOS transistors as memory cells, a bipolar transistor, and a resistance, said bipolar transistor having a base, emitter and collector; a plurality of bit lines for reading out data from the memory cells in a row; and a plurality of word lines for selecting the memory cells in a column, wherein a predetermined number of the basic cells are grouped into one memory block, each memory block containing a plurality of MOS transistors of the same conductivity type, and not containing any MOS transistors of any other conductivity type, the bipolar transistor and the resistance in each basic cell is used for each memory block as a driver for reading out data from the memory cells in the same memory block, the memory cells in the same memory block are connected to the base of the bipolar transistor and one side of the resistance, and the emitter of the bipolar transistor is connected to the other side of the resistance and the bit line through which data from the memory cells is transferred to outside of the semiconductor integrated circuit.

Claim 3

A semiconductor integrated circuit of the gate array type, comprising a plurality of basic cells arranged in a matrix, each of the basic cells comprising a plurality of MOS transistors as memory cells, a bipolar transistor, and a resistance, said bipolar transistor having a base, emitter and collector; a plurality of bit lines for reading out data from the memory cells in a row; and a plurality of word lines for selecting the memory cells in a column, wherein a predetermined number of the basic cells are grouped into one memory block, each memory block containing a plurality of MOS transistors of the same conductivity type, and not containing any MOS transistors of any other conductivity type, the bipolar transistor and the resistance in each basic cell is used for each memory block as a driver for reading out data from the memory cells in the same memory block, the memory cells in the same memory block are connected to the base of the bipolar transistor and one side of the resistance, and the emitter of the bipolar transistor is connected to the other side of the resistance and the bit line through which data from the memory cells is transferred to outside of the semiconductor integrated circuit, and wherein the electrical level of the bit lines are at a logic state "0" before the reading operation.

Claim 4

A semiconductor integrated circuit of the gate array type, comprising a plurality of basic cells arranged in a matrix, each of the basic cells comprising a plurality of MOS transistors as memory cells, a bipolar transistor, and a resistance, said bipolar transistor having a base, emitter and collector; a plurality of bit lines for reading out data from the memory cells in a row; and a plurality of word lines for selecting the memory cells in a column, wherein a predetermined number of the basic cells are grouped into one memory block, each memory block containing a plurality of MOS transistors of the same conductivity type, and not containing any MOS transistors of any other conductivity type, the bipolar transistor and the resistance in each basic cell is used for each memory block as a driver for reading out data from the memory cells in the same memory block, the memory cells in the same memory block are connected to the base of the bipolar transistor and one side of the resistance, and the emitter of the bipolar transistor is connected to the other side of the resistance and the bit line through which data from the memory cells is transferred to outside of the semiconductor integrated circuit, and wherein the electrical level of the bit lines are at a logic state "0" before the reading operation.

Claim 5

A semiconductor integrated circuit of the gate array type comprising: a plurality of basic cells arranged in matrix, each of the basic cells comprising: a plurality of MOS transistors as memory cells; a bipolar transistor of the NPN type or the PNP type; a resistance; a plurality of bit lines for reading out data from the memory calls in a row; and a plurality of word lines for selecting the memory cells in a column; wherein; a predetermined number of the basic cells are grouped into one memory block, the bipolar transistors of the NPN type and the PNP type and the resistance in adjacent basic cells are used for each memory block as a driver for reading out data from the memory cells in the same memory block, the memory cells in the memory group are connected to the base side of the bipolar transistors of NPN type and PNP type and the one side of the resistance, and the emitter of the bipolar MOS transistor of NPN type is connected to the emitter of the bipolar transistor of PNP type and the other side of the resistance and the bit line through which data from the memory cells in the same memory block is transferred to outside of the semiconductor integrated circuit.

Claim 6

A semiconductor integrated circuit of the gate array type comprising: a plurality of basic cells arranged in matrix, each of the basic cells comprising: a plurality of MOS transistors as memory cells; a bipolar transistor of the NPN type or the PNP type; a resistance; a plurality of bit lines for reading out data from the memory calls in a row; and a plurality of word lines for selecting the memory cells in a column; wherein; a predetermined number of the basic cells are grouped into one memory block, the bipolar transistors of the NPN type and the PNP type and the resistance in adjacent basic cells are used for each memory block as a driver for reading out data from the memory cells in the same memory block, the memory cells in the memory group are connected to the base side of the bipolar transistors of NPN type and PNP type and the one side of the resistance, and the emitter of the bipolar MOS transistor of NPN type is connected to the emitter of the bipolar transistor of PNP type and the other side of the resistance and the bit line through which data from the memory cells in the same memory block is transferred to outside of the semiconductor integrated circuit.

Claim 7

A semiconductor integrated circuit according to claim 3, wherein a higher electrical level "1" is transferred to the bit line by the emitter of the bipolar transistor of the NPN type when the memory cell stores the higher electrical level "1".

Claim 8

A semiconductor integrated circuit of the gate array type, comprising: a plurality of basic cells arranged in a matrix, each of the basic cells comprising a plurality of N-type MOS transistors and a plurality of P-type MOS transistors as memory cells, a resistance, and a bipolar transistor having a base, an emitter, and a collector; a plurality of bit lines for reading out data from the memory cells in a row; and a plurality of word lines for selecting the memory cells in a column, wherein said semiconductor integrated circuit is formed as a plurality of memory blocks, each of said memory blocks including parts of a predetermined number of basic cells, each of said memory blocks containing at least one of said bipolar transistors, at least one of said resistances, and a plurality of either said N-type MOS transistors or said P-type MOS transistors, but not both, said at least one of said bipolar transistors and resistances in each of said memory blocks is used as a driver for reading out data from the memory cells in each of said memory blocks, the memory cells in each of said memory blocks are connected to the base of the bipolar transistor and one side of the resistance, and the emitter of the bipolar transistor is connected to the other side of the resistance and the bit line through which data from the memory cells is transferred to outside of the semiconductor integrated circuit.

Claim 9

A semiconductor integrated circuit of the gate array type, comprising: a plurality of basic cells arranged in a matrix, each of the basic cells comprising a plurality of N-type MOS transistors and a plurality of P-type MOS transistors as memory cells, a resistance, and a bipolar transistor having a base, an emitter, and a collector; a plurality of bit lines for reading out data from the memory cells in a row; and a plurality of word lines for selecting the memory cells in a column, wherein said semiconductor integrated circuit is formed as a plurality of memory blocks, each of said memory blocks including parts of a predetermined number of basic cells, each of said memory blocks containing at least one of said bipolar transistors, at least one of said resistances, and a plurality of either said N-type MOS transistors or said P-type MOS transistors, but not both, said at least one of said bipolar transistors and resistances in each of said memory blocks is used as a driver for reading out data from the memory cells in each of said memory blocks, the memory cells in each of said memory blocks are connected to the base of the bipolar transistor and one side of the resistance, and the emitter of the bipolar transistor is connected to the other side of the resistance and the bit line through which data from the memory cells is transferred to outside of the semiconductor integrated circuit.