US5444014A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating semiconductor device
Assignee: Electronics and Telecommunications Research Institute
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Filing: 1994-12-16
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Granted: 1995-08-22
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Expires: 2014-12-16
Abstract
Abstract Disclosed is a method of fabricating an SOI substrate, comprising the steps of forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region 31 as the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. By the method, a stray capacitance occurring between an SOI substrate and a metal wiring portion formed thereon can be significantly reduced owing to a relatively thick insulating layer therebetween, and a parasitic capacitance can be eliminated owing to an insulating layer interposed between a bonding substrate and an active region to be used as a buried collector.
Inventors
- 👤 Byung-Ryul Ryum
- 👤 Tae-Hyeon Han
- 👤 Soo-Min Lee
- 👤 Deok-Ho Cho
- 👤 Seong-Hearn Lee
- 👤 Jin-Young Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:38
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/054; H10D10/041; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/018; H10W10/061; H10W10/10; H10W10/181; H10P90/1914; H10W10/014; H10W10/041; H10W10/17; H10W10/40; Y; Y10; Y10S; Y10S148/00; Y10S148/012
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
102 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region using the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region.
Claim 2
Independent Claim
102 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form an opening; growing a single crystal silicon in the opening to form active and inactive regions; polishing the active region using the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; and polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region.
Claim 3
Dependent Claim
17 words
The method according to claim 1, wherein the first insulating layer is composed of a multi-layer structure.
Claim 4
Dependent Claim
43 words
The method according to claim 2, wherein the multi-layer structure is formed by the step of sequentially forming a silicon oxide layer of about 500 Å thickness, a polysilicon layer of about 0.1 μm and a thick oxide layer on the silicon substrate.
Claim 5
Independent Claim
251 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form a first opening; growing a single crystal silicon in the first opening to form active and intrinsic regions; polishing the active region using the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. introducing an impurity into the active region to form a buried collector region; depositing a patterned oxide layer having a second opening on the planarized surface; growing a single crystal silicon layer doped with an impurity in the second opening to form a collector; forming a silicide layer only on the collector; forming an extrinsic base only on a portion of the patterned oxide layer; depositing a third insulating layer having a third opening thereon, the third opening being formed on the silicide layer; forming a first side wall on both sides of the third opening; removing the silicide layer and forming an intrinsic base at a region where the silicide layer is removed; forming a second side wall on the first side wall; forming an emitter on the intrinsic base in the third opening; and forming electrodes to be respectively connected to the emitter, collector and base.
Claim 6
Independent Claim
251 words
A method for fabricating a semiconductor device, comprising the steps of: forming a first insulating layer on a single crystal silicon substrate; patterning the first insulating layer to form a first opening; growing a single crystal silicon in the first opening to form active and intrinsic regions; polishing the active region using the first insulating layer as a polishing stopper to form a planarized surface; depositing a second insulating layer on the planarized surface; bonding a bonding substrate to the second insulating layer; polishing the silicon substrate using the first insulating layer as a stopper up to a surface of the active region. introducing an impurity into the active region to form a buried collector region; depositing a patterned oxide layer having a second opening on the planarized surface; growing a single crystal silicon layer doped with an impurity in the second opening to form a collector; forming a silicide layer only on the collector; forming an extrinsic base only on a portion of the patterned oxide layer; depositing a third insulating layer having a third opening thereon, the third opening being formed on the silicide layer; forming a first side wall on both sides of the third opening; removing the silicide layer and forming an intrinsic base at a region where the silicide layer is removed; forming a second side wall on the first side wall; forming an emitter on the intrinsic base in the third opening; and forming electrodes to be respectively connected to the emitter, collector and base.
Claim 7
Dependent Claim
28 words
The method according to claim 4, wherein the step of injection the impurity comprises injecting the impurity having a concentration of more than 5×10 18 cm -3 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-21 | 1999-02-20 | 1999-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-21 | 2003-02-20 | 2003-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-21 | 2007-02-20 | 2007-08-22 | $7700.00 | Window Closed / Lapsed |