Patent US1180680A successfully refreshed from Google Patents.
Patent US5442402A successfully refreshed from Google Patents.
US5442402A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Modular memory for an image decoding system
Assignee: WiniaDaewoo Co Ltd
•
Filing: 1993-09-23
•
Granted: 1995-08-15
•
Expires: 2013-09-23
Abstract
Abstract A high speed modular memory adapted for use in a decoding system of motion compensated prediction coded image data, comprises: 2 N memory modules each comprising a two dimensional memory array with an address register for storing different pixels of a frame of the image data, wherein said N is a positive integer; a read/write signal generator for generating a read/write signal in response to a frame synchronization signal from the image data; an address generator for simultaneously generating a horizontal and a vertical addresses for each of the 2 N memory modules in response to a motion vector separated into a horizontal motion vector and a vertical motion vector and the read/write control signal; a data bus for communicating the image data with the 2 N memory modules; and an order changer which changes within the data bus positions of the data simultaneously read from the 2 N memory modules within the data bus in response to the horizontal motion vector.
Inventors
- 👤 Chang Sohn
- 👤 Oh-Sang Kwon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 14:46
CPC Classifications
H; H04; H04N; H04N19/00; H04N19/42; H04N19/423; H04N21/00; H04N21/20; H04N21/23; H04N21/231; H04N19/436; H04N19/60; H04N19/61
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
198 words
A modular memory for use in a decoding system of motion compensated prediction coded image data, comprising: 2 N memory modules each comprising a two dimensional memory array for storing different pixels of a frame of the image data in accordance with horizontal locations of the different pixels within the frame, wherein N is a positive integer; means for generating a read/write signal in response to a frame synchronization signal from the image data; an address generator for simultaneously generating a read/write horizontal and a read/write vertical addresses for each of the 2 N memory modules in response to a motion vector from the image data and the read/write signal; a parallel data bus for simultaneously outputting/inputting 2 N pixels of the image data from/into the 2 N memory modules in response to the read/write signal; and means for, before outputting the 2 N pixels, changing relative positions of the 2 N pixels with each other in the parallel data bus in response to a horizontal component of the motion vector so that the 2 N pixels are arranged in the parallel data bus in ascending order of horizontal locations of the 2 N pixels within the frame.
Claim 2
Dependent Claim
198 words
A modular memory for use in a decoding system of motion compensated prediction coded image data, comprising: 2 N memory modules each comprising a two dimensional memory array for storing different pixels of a frame of the image data in accordance with horizontal locations of the different pixels within the frame, wherein N is a positive integer; means for generating a read/write signal in response to a frame synchronization signal from the image data; an address generator for simultaneously generating a read/write horizontal and a read/write vertical addresses for each of the 2 N memory modules in response to a motion vector from the image data and the read/write signal; a parallel data bus for simultaneously outputting/inputting 2 N pixels of the image data from/into the 2 N memory modules in response to the read/write signal; and means for, before outputting the 2 N pixels, changing relative positions of the 2 N pixels with each other in the parallel data bus in response to a horizontal component of the motion vector so that the 2 N pixels are arranged in the parallel data bus in ascending order of horizontal locations of the 2 N pixels within the frame.
Claim 3
Dependent Claim
40 words
The modular memory of claim 1, wherein each of the 2 N memory modules stores the different pixels each having a same value A as determined by A=(a horizontal location of a pixel within the frame) modulo 2 N .
Claim 4
Dependent Claim
41 words
The modular memory of claim 2, wherein said means for changing relative positions of the 2 N pixels includes 2 N multiplexors with the least significant N bits of the horizontal component of the motion vector as a selection input thereof.
Claim 5
Dependent Claim
210 words
The modular memory of claim 2 or 3, wherein said address generator includes: a pixel clock; means for generating a base vertical address in response to the pixel clock; means for generating a base horizontal address in response to the pixel clock; means for generating a modified vertical address for each of the 2 N memory modules by adding a vertical component of the motion vector to the base vertical address; means for generating a carry signal for each of 2 N -1 memory modules of the 2 N memory modules in response to the least significant N bits of the horizontal component of the motion vector; means for generating a modified horizontal address for each of the 2 N memory modules by adding the horizontal component of the motion vector truncated its least significant N bits to the base horizontal address with a respective one of the carry signals. means for providing the modified vertical address/the base vertical address as the read/write vertical address for each of the 2 N memory modules in response to the read/write signal; and means for providing address the modified horizontal address/the base horizontal address as the read/write horizontal address for each of the 2 N memory modules in response to the read/write signal.
References Cited (Backward Citations)
US4189767A
Cited
US4766496A
Cited
US4776025A
Cited
US5068650A
Cited
US4998167A
Cited
US5220425A
Cited
US5227882A
Cited
US5315388A
Cited
US5373323A
Cited
US5376973A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-14 | 1999-02-13 | 1999-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-14 | 2003-02-13 | 2003-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-14 | 2007-02-13 | 2007-08-15 | $7700.00 | Window Closed / Lapsed |