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US5440711A
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Method for controlling DRAM memory in a microcomputer
Assignee: Mitsubishi Electric Corp
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Filing: 1993-12-13
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Granted: 1995-08-08
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Expires: 2013-12-13
Abstract
Abstract There is provided a microcomputer including therein a DRAM controller, the DRAM controller including a refresh controller for refreshing a DRAM and an access controller for controlling the access to the DRAM whereby the need of a DRAM controlling external circuit that suffers from severe timing adjustment is eliminated and hence the DRAM is made directly connectable to the microcomputer.
Inventors
- 👤 Masaki Sugimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:12
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
159 words
A method for operating a computer having a memory, the method comprising the steps of: defining a portion of said memory as an active memory space by asserting a plurality of area selection bits whereby the remainder of said memory is an inactive memory space; asserting a memory access effective bit, said bit for permitting access to said memory space and for controlling generation of row address strobe (RAS) and column address strobe (CAS) signals; asserting a refresh request to refresh said active memory space; asserting a CPU memory access request to said active memory space; arbitrating between said refresh request and said CPU memory access request; delaying, at least until refresh of said active memory space is complete, the CPU memory access request when said CPU memory access request requests data in said active memory space; and refreshing said memory, including said active and said inactive memory space, by asserting said CAS signal before asserting said RAS signal.
Claim 2
Independent Claim
159 words
A method for operating a computer having a memory, the method comprising the steps of: defining a portion of said memory as an active memory space by asserting a plurality of area selection bits whereby the remainder of said memory is an inactive memory space; asserting a memory access effective bit, said bit for permitting access to said memory space and for controlling generation of row address strobe (RAS) and column address strobe (CAS) signals; asserting a refresh request to refresh said active memory space; asserting a CPU memory access request to said active memory space; arbitrating between said refresh request and said CPU memory access request; delaying, at least until refresh of said active memory space is complete, the CPU memory access request when said CPU memory access request requests data in said active memory space; and refreshing said memory, including said active and said inactive memory space, by asserting said CAS signal before asserting said RAS signal.
Claim 3
Dependent Claim
42 words
The method of claim 1, wherein said step of arbitrating further comprises the steps of: using a register to count cycles of an internal clock; and assigning priority to and executing said refresh request when said register is in an overflow condition.
Claim 4
Dependent Claim
30 words
The method of claim 1 further comprising the step of executing said CPU access request by activating an access signal generator to strobe a row address and a column address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |