Data processor having branch predicting function

Claim 2

A data processor including a central processing unit (CPU) and memory for executing instructions including a conditional branch instruction, said data processor having a branch predicting function, comprising: fetching and decoding means for fetching and decoding said conditional branch instruction stored at a predetermined address in said memory and supplying an instruction length of said conditional branch instruction and a branch displacement specified by a branch displacement portion of said conditional branch instruction, instruction executing means for executing said conditional branch instruction decoded by said fetching and decoding means, branch predicting means for supplying a prediction signal indicating if said conditional branch instruction is predicted to result in taking a branch or not taking a branch, first replacing means responsive to said prediction signal for replacing said instruction length with said branch displacement, and second replacing means responsive to said prediction signal for replacing said branch displacement with said instruction length, a branch operation being executed by said instruction executing means to a destination specified by the predetermined address of said conditional branch instruction incremented by said instruction length in response to (i) a prediction by said predicting means of taking a branch and (ii) said prediction being found to be incorrect when said conditional branch instruction has been executed by said instruction executing means, said second radiating means including a first register for storing the instruction length decoded by said fetching and decoding means, a second register for storing the displacement decoded said fetching and decoding means, and first selecting means, responsive to said prediction signal for supplying the instruction length stored in said first register to said instruction executing means.

Claim 3

A data processor in accordance with claim 1, wherein said fetching and decoding means comprises an instruction register for storing said conditional branch instruction, and an instruction decoder for decoding the conditional branch instruction stored in said instruction register and supplying said instruction length and said branch displacement to said instruction executing means and to said replacing means.

Claim 4

A data processor in accordance with claim 1, wherein said branch predicting means comprises means for storing a predicting bit for predicting whether or not said conditional branch instruction will result in execution of a branch operation.

Claim 5

A data processor in accordance with claim 1, further comprising: address counting means for counting addresses to address a next instruction, and adder means receiving an address value from said address counting means and adding to said address value said displacement selected by said first selecting means to form a next instruction address and supplying said next instruction address to said address counting means.

Claim 6

A data processor in accordance with claim 1, wherein said first selecting means comprises means responsive to said prediction signal for supplying the instruction length stored in said first register when no branch is predicted by said branch predicting means.

Claim 7

A data processor in accordance with claim 1, wherein said second replacing mean comprises a third register for storing the instruction length decoded by said fetching and decoding means, a fourth register for storing the displacement decoded by said fetching and decoding means, and second selecting means responsive to said prediction signal for selecting the displacement stored in said fourth register.

Claim 8

A data processor in accordance with claim 6, wherein said second selecting means comprises means responsive to said prediction signal for supplying the displacement stored in said fourth register to said instruction executing means when no branch is predicted by said branch predicting means.

Claim 9

A data processor in accordance with claim 1, wherein said second replacing means comprises branch condition changing means for changing a branch condition of said conditional branch instruction, in response to said prediction signal.

Claim 10

A data processor in accordance with claim 8, wherein said second replacing means comprises inverter means for inverting a true branch condition bit signal of said conditional branch instruction to generate an inverted branch condition bit signal and a selector means for selecting one of said true branch condition bit signal and said inverted branch condition bit signal in response to said prediction signal.

Claim 11

A data processor in accordance with claim 1, wherein said second replacing means forms a modified instruction and supplies said modified instruction to said instruction executing means.

Claim 12

A data processor in accordance with claim 1, wherein said first replacing means includes a first register for storing said instruction length and a second register for storing said branch displacement; and said first replacing means providing an address of the next instruction to be executed by (a) using said branch displacement stored in said second register when said conditional branch instruction is correctly predicted to result in taking a branch, (b) using said instruction length stored in said first register when said conditional branch instruction is correctly predicted to result in not taking a branch, said second replacing means providing an address of a next instruction to be executed, (c) using said instruction length stored in said fourth register when said conditional branch instruction is incorrectly predicted to result in taking a branch, and (d) using said branch displacement stored in said third register when said conditional branch instruction is incorrectly predicted to result in not taking a branch.

Claim 13

A data processor in accordance with claim 1, wherein said first replacing means includes a first register storing said instruction length and a second register storing said branch displacement; and said first replacing means supplying an address of a next instruction to be executed responsive to said branch prediction signal from said branch predicting means and to the execution of a branching operation by said instruction execution means, said address of said next instruction being selectively retrieved from (a) said second register when said conditional branch instruction is correctly predicted to result in taking a branch, (b) said first register when said conditional branch is correctly predicted to result in not taking a branch, (c) said fourth register when said conditional branch is incorrectly predicted to result in taking a branch, and (d) said third register when said conditional branch instructions is incorrectly predicted to result in not taking a branch.

Claim 14

A data processor for executing instructions including a conditional branch instruction, said data processor having a branch predicting function, comprising: fetching and decoding means for fetching and decoding said conditional branch instruction stored at a predetermined address and supplying an instruction length of said conditional branch instruction and a branch displacement specified by a branch displacement portion of said conditional branch instruction, instruction executing means for executing said conditional branch instruction decoded by said fetching and decoding means, branch predicting means responsive to said predetermined address of said conditional branch instruction for supplying a prediction signal indicating if said conditional branch instruction is predicted to result in taking a branch, and replacing means responsive to said prediction signal for replacing said branch displacement with said instruction length to form a modified instruction and supplying said modified instruction to said instruction executing means, a branch operation being executed by said instruction executing means to a destination specified by the predetermined address of said conditional branch instruction incremented by said instruction length in response to (i) a prediction by said predicting means of taking a branch and (ii) said prediction being found to be incorrect when said conditional branch instruction has been executed by said instruction executing means.

Claim 15

A data processor for executing instructions including a conditional branch instruction, said data processor having a branch predicting function, comprising: fetching and decoding means for fetching and decoding said conditional branch instruction stored at a predetermined address and supplying an instruction length of said conditional branch instruction and a branch displacement specified by a branch displacement portion of said conditional branch instruction, instruction executing means for executing said conditional branch instruction decoded by said fetching and decoding means, branch predicting means responsive to said predetermined address of said conditional branch instruction for supplying a prediction signal indicating if said conditional branch instruction is predicted to result in taking a branch, and replacing means responsive to said prediction signal for replacing said branch displacement with said instruction length to form a modified instruction and supplying said modified instruction to said instruction executing means, a branch operation being executed by said instruction executing means to a destination specified by the predetermined address of said conditional branch instruction incremented by said instruction length in response to (i) a prediction by said predicting means of taking a branch and (ii) said prediction being found to be incorrect when said conditional branch instruction has been executed by said instruction executing means.

Claim 16

A data processor for executing a series of instructions stored in a plurality of memory addresses, said instructions including a conditional branch instruction having instruction code data and branch offset data, said data processor comprising: a decode address register for storing a current address of said conditional branch instruction currently decoded and responsive to an increment value for supplying a next address of an instruction to be decoded; branch predicting means responsive to said current address of said conditional branch instruction currently decoded for supplying a branch prediction signal; a first selector responsive to said branch prediction signal for selectively supplying to said decode address register as said increment value (i) an instruction length of said conditional branch instruction currently decoded in response to a prediction that no-branch will result and (ii) said branch offset data of said conditional branch instruction currently decoded in response to a prediction that a branch will result; an instruction register responsive to said current address of said conditional branch instruction currently decoded for storing a current instruction to be decoded; an instruction decoder responsive to said current instruction to be decoded for supplying (i) a plurality of condition code bit signals and (ii) a branch/no-branch on condition bit signal; a central processor including (i) a program counter register for storing an address of an instruction to be executed, (ii) program counter incrementing means responsive to said address of said instruction to be executed and to a program counter increment value for storing in said program counter register an address of an instruction to be next executed, and (iii) branching means responsive to said plurality of condition code bit signals and said branch/no-branch on condition bit signal for storing a branch address in said program counter register as said address of an instruction to be next executed; a second selector responsive to said branch prediction signal for selectively supplying to said central processor as said program counter increment value (i) an instruction length of said conditional branch instruction currently decoded in response to a prediction that a branch will result and (ii) said branch offset data of said conditional branch instruction currently decoded in response to a prediction that no-branch will result; and inverter means for selectively inverting said branch/no-branch on condition signal in response to said branch prediction signal and supplying said selectively inverted branch/no-branch on condition signal to said branching means of said central processor.

Claim 17

A data processor for executing a series of instructions stored in a plurality of memory addresses, said instructions including a conditional branch instruction having instruction code data and branch offset data, said data processor comprising: a decode address register for storing a current address of said conditional branch instruction currently decoded and responsive to an increment value for supplying a next address of an instruction to be decoded; branch predicting means responsive to said current address of said conditional branch instruction currently decoded for supplying a branch prediction signal; a first selector responsive to said branch prediction signal for selectively supplying to said decode address register as said increment value (i) an instruction length of said conditional branch instruction currently decoded in response to a prediction that no-branch will result and (ii) said branch offset data of said conditional branch instruction currently decoded in response to a prediction that a branch will result; an instruction register responsive to said current address of said conditional branch instruction currently decoded for storing a current instruction to be decoded; an instruction decoder responsive to said current instruction to be decoded for supplying (i) a plurality of condition code bit signals and (ii) a branch/no-branch on condition bit signal; a central processor including (i) a program counter register for storing an address of an instruction to be executed, (ii) program counter incrementing means responsive to said address of said instruction to be executed and to a program counter increment value for storing in said program counter register an address of an instruction to be next executed, and (iii) branching means responsive to said plurality of condition code bit signals and said branch/no-branch on condition bit signal for storing a branch address in said program counter register as said address of an instruction to be next executed; a second selector responsive to said branch prediction signal for selectively supplying to said central processor as said program counter increment value (i) an instruction length of said conditional branch instruction currently decoded in response to a prediction that a branch will result and (ii) said branch offset data of said conditional branch instruction currently decoded in response to a prediction that no-branch will result; and inverter means for selectively inverting said branch/no-branch on condition signal in response to said branch prediction signal and supplying said selectively inverted branch/no-branch on condition signal to said branching means of said central processor.