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US5440280A
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Digital microwave multi-bit attenuator
Assignee: IMT COMMUNICATIONS SYSTEMS Inc
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Filing: 1993-09-17
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Granted: 1995-08-08
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Expires: 2013-09-17
Abstract
Abstract An attenuator circuit having a resistive "T" network and a resistive "Pi network in parallel with said "T" network.
Inventors
- 👤 J. L. Martin Lord
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:43
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/24; H03H11/245
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
85 words
A wideband digital microwave attenuator circuit formed on a semiconductor substrate, comprising: (a) a resistive "T" network having a signal input terminal and a signal output terminal; and (b) a resistive "Pi" network having a signal input terminal and signal output terminal such that only the signal input and signal output terminals of said "T" network are connected to the signal input and signal output terminals, respectively, of said "Pi" network, whereby to place said resistive "Pi" network in parallel with said resistive "T" network.
Claim 2
Dependent Claim
85 words
A wideband digital microwave attenuator circuit formed on a semiconductor substrate, comprising: (a) a resistive "T" network having a signal input terminal and a signal output terminal; and (b) a resistive "Pi" network having a signal input terminal and signal output terminal such that only the signal input and signal output terminals of said "T" network are connected to the signal input and signal output terminals, respectively, of said "Pi" network, whereby to place said resistive "Pi" network in parallel with said resistive "T" network.
Claim 3
Dependent Claim
31 words
A circuit according to claim 1, wherein said "T" and "Pi" networks each have switching elements and switching means for changing the resistive state of at least some of said elements.
Claim 4
Dependent Claim
82 words
A circuit according to claim 1, wherein said "T" and "Pi" networks each have a plurality of branches and switching elements in each of said branches, control signal lines coupled to each of said switching elements for conducting control signals to cause reversible switching of said elements from an "ON" to an "OFF" condition, the switching of said elements operative to adjust the resistance in each branch of said "Pi" and "T" networks and thereby change the attenuation level of said circuit.
Claim 5
Dependent Claim
45 words
A circuit according to claim 3, wherein each of said branches of said "Pi" and "T" networks has multiple resistance paths and including switching elements in said paths to reversibly switch the resistance of the paths from a high impedance to a lower impedance value.
Claim 6
Dependent Claim
12 words
A circuit according to claim 4, wherein said switching elements are FETS.
Claim 7
Dependent Claim
16 words
A circuit according to claim 4, wherein each of said branches has at least two paths.
Claim 8
Dependent Claim
22 words
A circuit according to claim 4, including a 4-bit parallel "Pi" and "T" network cascaded with a 1-bit "Pi" and "T" network.
Claim 9
Dependent Claim
23 words
A circuit according to claim 1, including a digital multiplexer and encoder interfacing a parallel bit stream source of signals with said circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-08-07 | 1999-02-06 | 1999-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-08-07 | 2003-02-06 | 2003-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-08-07 | 2007-02-06 | 2007-08-08 | $7700.00 | Window Closed / Lapsed |