Semiconductor integrated circuit device and data processing system having an interface with reduced parasitic capacitance

Claim 2

A semiconductor integrated circuit device formed on a semiconductor region, comprising: an external terminal; first output switching means including a first output region on the semiconductor region, for providing output data in accordance with a signal from an internal logic circuit having a predetermined logic function, to the first output region thereof; first Schottky diode means connected between the external terminal and the first output region of the first output switching means, for removing a parasitic capacitance of the first output region from the external terminal when the first output switching means is turned-off; and input means connected to the external terminal, for receiving input data transmitted through the external terminal.

Claim 3

A semiconductor integrated circuit device according to claim 1, wherein the external terminal is connected with a transmission line terminated by impedance elements.

Claim 4

A semiconductor integrated circuit device according to claim 2, wherein the transmission line has each of its two terminals supplied with a terminal voltage through the impedance elements.

Claim 5

A semiconductor integrated circuit device according to claim 3, wherein the first output switching means includes an open-drain type output MOSFET; and wherein the first output region is a drain region of the open-drain type output MOSFET.

Claim 6

A semiconductor integrated circuit device according to claim 4, further comprising drive means for driving the open-drain type output MOSFET in accordance with the signal from the internal logic circuit.

Claim 7

A semiconductor integrated circuit device according to claim 5, wherein the open-drain type output MOSFET has its gate fed with an output signal from the drive means.

Claim 8

A semiconductor integrated circuit device according to claim 6, wherein the first Schottky diode means is integrally formed in alignment with a contact hole provided between the drain region of the open-drain type MOSFET and the external terminal.

Claim 9

A semiconductor integrated circuit device according to claim 7, wherein the impedance elements are resistors.

Claim 10

A semiconductor integrated circuit device according to claim 6, further comprising second output switching means including a second output region on the semiconductor region, for providing the output data in accordance with the signal from the internal logic circuit having the predetermined logic function, to the second output region thereof, at a slower timing than that of the first output switching means; and second Schottky diode means connected between the external terminal and the second output region of the second output switching means, for removing a parasitic capacitance of the second output region from the external terminal when the second output switching means is turned-off.

Claim 11

A semiconductor integrated circuit device according to claim 9, further comprising third output switching means connected between including a third output region on the semiconductor region, for providing the output data in accordance with the signal from the internal logic circuit having the predetermined logic function, to the third output region thereof, at a slower timing than that of the second output switching means.

Claim 12

A data processing system comprising: a first semiconductor integrated circuit device formed on a first semiconductor region including: a first external terminal; and a first output switching element having a first output region on the first semiconductor region and providing first output data, in accordance with a first signal from a first internal logic circuit in the first semiconductor integrated circuit device, to the first output region; a transmission line connected with the first external terminal; and a second semiconductor integrated circuit device formed on a second semiconductor region including: a second external terminal coupled to the transmission line; a second output switching element having a second output region on the second semiconductor region, and providing second output data, in accordance with a second signal from a second internal logic circuit in the second semiconductor integrated circuit device, to the second output region; a first input buffer connected with the second external terminal, which receives input data transmitted from the transmission line through the second external terminal; and a first one-way element connected between the second external terminal and the second output region of the second output switching element, to remove a parasitic capacitance of the second output region from the second external terminal when the second output switching element is turned-off, wherein the transmission line has its two terminals supplied with terminal voltages individually through impedance elements.

Claim 13

A data processing system comprising: a first semiconductor integrated circuit device formed on a first semiconductor region including: a first external terminal; and a first output switching element having a first output region on the first semiconductor region and providing first output data, in accordance with a first signal from a first internal logic circuit in the first semiconductor integrated circuit device, to the first output region; a transmission line connected with the first external terminal; and a second semiconductor integrated circuit device formed on a second semiconductor region including: a second external terminal coupled to the transmission line; a second output switching element having a second output region on the second semiconductor region, and providing second output data, in accordance with a second signal from a second internal logic circuit in the second semiconductor integrated circuit device, to the second output region; a first input buffer connected with the second external terminal, which receives input data transmitted from the transmission line through the second external terminal; and a first one-way element connected between the second external terminal and the second output region of the second output switching element, to remove a parasitic capacitance of the second output region from the second external terminal when the second output switching element is turned-off, wherein the transmission line has its two terminals supplied with terminal voltages individually through impedance elements.

Claim 14

A data processing system according to claim 11, wherein each of the first and second output switching elements includes an open-drain type output MOSFET, and wherein each of the first and second output regions is a drain region of the open-drain type output MOSFET.

Claim 15

A data processing system according to claim 12, wherein the first semiconductor integrated circuit device has a second one-way element connected between the first external terminal and the drain region of the open-drain type output MOSFET in the first output switching element.

Claim 16

A data processing system according to claim 13, further comprising: a first drive circuit which drives the open-drain type output MOSFET of the first output switching element in accordance with the first signal, wherein the open-drain type output MOSFET of the first output switching element has its gate fed with a first output signal from the first drive circuit, and a second drive circuit which drives the open-drain type output MOSFET of the second output switching element in accordance with the second signal, wherein the open-drain type output MOSFET of the second output switching element has its gate fed with a second output signal from the second drive circuit.

Claim 17

A data processing system according to claim 14, wherein each of the first and second one-way elements is a Schottky diode, and wherein the impedance elements are resistors.

Claim 18

A data processing system according to claim 15, wherein the first input buffer is a differential configuration circuit which compares the input data with a reference voltage.

Claim 19

A data processing system according to claim 13, wherein the first semiconductor integrated circuit device has a second input buffer connected with the first external terminal.

Claim 20

A data processing system according to claim 17, wherein each of the first and second one-way elements is a Schottky diode, and wherein the impedance elements are resistors.

Claim 21

A data processing system according to claim 18, wherein each of the first and second input buffers is a differential configuration circuit which compares the input data with a reference voltage.

Claim 22

A data processing system according to claim 8, wherein the input means includes a differential configuration circuit which compares the input data with a reference voltage.

Claim 23

A semiconductor integrated circuit device formed on a semiconductor region comprising: an external terminal; an output switching element including an output region on the semiconductor region and providing output data, in accordance with a signal from an internal logic circuit having a predetermined logic function, to the output region thereof; an input buffer connected with the external terminal, which receives input data transmitted through the external terminal; and a one-way element connected between the external terminal and the output region of the output switching element, to remove a parasitic capacitance of the output region from the external terminal when the output switching element is turned-off.

Claim 24

A semiconductor integrated circuit device formed on a semiconductor region comprising: an external terminal; an output switching element including an output region on the semiconductor region and providing output data, in accordance with a signal from an internal logic circuit having a predetermined logic function, to the output region thereof; an input buffer connected with the external terminal, which receives input data transmitted through the external terminal; and a one-way element connected between the external terminal and the output region of the output switching element, to remove a parasitic capacitance of the output region from the external terminal when the output switching element is turned-off.

Claim 25

A semiconductor integrated circuit device according to claim 21, wherein the external terminal is connected to a transmission line terminated by impedance elements, and wherein the transmission line has two terminals, each of which is supplied with a terminal voltage through the impedance elements.

Claim 26

A semiconductor integrated circuit device according to claim 22, wherein the output switching element includes an open-drain type MOSFET, and wherein the output region is a drain region of the open-drain type output MOSFET.

Claim 27

A semiconductor integrated circuit device according to claim 23, further comprising drive circuit which drives the open-drain type output MOSFET in accordance with the signal from the internal logic circuit.

Claim 28

A semiconductor integrated circuit device according to claim 24, wherein the open-drain type output MOSFET has its gate fed with an output signal from the drive circuit.

Claim 29

A semiconductor integrated circuit device according to claim 25, wherein the one-way element is integrally formed in alignment with a contact hole provided between the drain region of the open-drain type MOSFET and the external terminal.

Claim 30

A semiconductor integrated circuit device according claim 26, wherein the one-way element is a Schottky diode, and wherein the impedance elements are resistors.

Claim 31

A semiconductor integrated circuit device according to claim 27, wherein the input buffer is a differential configuration circuit which compares the input data with a reference voltage.

Claim 32

A data processing system comprising: a first semiconductor integrated circuit device formed on a first semiconductor region including: a first external terminal; a first output switching element having a first output region on the first semiconductor region and providing first output data, in accordance with a first signal from a first internal logic circuit in the first semiconductor integrated circuit device, to the first output region; and a first one-way element connected between the first external terminal and the first output region of the first output switching element, to remove a parasitic capacitance of the first output region from the first external terminal when the first output switching element is turned-off; a transmission line connected to the first external terminal; and a second semiconductor integrated circuit device formed on a second semiconductor region including: a second external terminal coupled to the transmission line; and a first input buffer connected with the second external terminal, the first input buffer receiving input data transmitted from the transmission line through the second external terminal, wherein the transmission line has two terminals, each of which is supplied with terminal voltages individually through impedance elements.

Claim 33

A data processing system comprising: a first semiconductor integrated circuit device formed on a first semiconductor region including: a first external terminal; a first output switching element having a first output region on the first semiconductor region and providing first output data, in accordance with a first signal from a first internal logic circuit in the first semiconductor integrated circuit device, to the first output region; and a first one-way element connected between the first external terminal and the first output region of the first output switching element, to remove a parasitic capacitance of the first output region from the first external terminal when the first output switching element is turned-off; a transmission line connected to the first external terminal; and a second semiconductor integrated circuit device formed on a second semiconductor region including: a second external terminal coupled to the transmission line; and a first input buffer connected with the second external terminal, the first input buffer receiving input data transmitted from the transmission line through the second external terminal, wherein the transmission line has two terminals, each of which is supplied with terminal voltages individually through impedance elements.

Claim 34

A data processing system according to claim 29, wherein the first output switching element includes an open-drain type output MOSFET, and wherein the first output region is a drain region of the open-drain type output MOSFET.

Claim 35

A data processing system according to claim 30, wherein the second semiconductor integrated circuit device includes: a second output switching element having a second output region on the second semiconductor region and providing second output data in accordance with a second signal from a second internal logic circuit in the second semiconductor integrated circuit device, to the second output region; and a second one-way element connected between the second external terminal and the drain region of the open-drain type output MOSFET in the second output switching element.

Claim 36

A data processing system according to claim 31, further comprising: a first drive circuit which drives the open-drain type output MOSFET of the first output switching element in accordance with the first signal; wherein the open-drain type output MOSFET of the first output switching element has its gate fed with a first output signal from the first drive circuit; and a second drive circuit which drives the open-drain type output MOSFET of the second output switching element in accordance with the second signal, wherein the open-drain type output MOSFET of the second output switching element has its gate fed with a second output signal from the second drive circuit.

Claim 37

A data processing system according to claim 32, wherein each of the first and second one-way elements is a Schottky diode, and wherein the impedance elements are resistors.

Claim 38

A data processing system according to claim 33, wherein the first input buffer is a differential configuration circuit which compares the input data with a reference voltage.

Claim 39

A data processing system according to claim 31, wherein the first semiconductor integrated circuit device has a second input buffer connected with the first external terminal.

Claim 40

A data processing system according to claim 35, wherein each of the first and second one-way elements is a Schottky diode, and wherein the impedance elements are resistors.

Claim 41

A data processing system according to claim 36, wherein each of the first and second input buffers is a differential configuration circuit which compares the input data with a reference voltage.