← Back to Patent Explorer
US3723759A Expired / Lapsed US ⏱️ 0.0 years remaining

Interface circuit

Assignee: Individual
•
Filing: 1971-04-26
•
Granted: 1973-03-27
•
Expires: 1991-04-26
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A circuit for rendering a binary source signal applied to the input of a TTL integrated circuit non-inverting gate to have the characteristics required by the gate for faultless operation as to voltage value and speed of change by a voltage dividing network and a feedback line from the output to the input of the gate. The gate input voltage is also clamped at high and low voltages.

Inventors

  • 👤 I Giguere

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-27 22:22
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/017509

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 186 words
An interface circuit for use with a transistor to transistor integrated circuit having a fast switching gate formed to have an input and an output and having an unstable region for selected values of voltages at the gate input, said gate providing binary information in the form of one of two different binary voltage levels at its output, and source mans having a lead for supplying binary information in the form of one of two voltage levels to the input with the gate output shifting its binary information as the source binary information on the lead shifts to maintain correlation therebetween, said interface circuit including a voltage divider having an end connected to the source means lead and another end connected to a D.C. source with an intermediate portion connected to the gate input and means for supplying a positive feedback voltage from the gate output to the gate input and in which there are means for preventing the value of the voltage at the gate input from substantially exceeding the values of voltage applied at the gate input required for the two different binary states.
Claim 2
Dependent Claim 186 words
An interface circuit for use with a transistor to transistor integrated circuit having a fast switching gate formed to have an input and an output and having an unstable region for selected values of voltages at the gate input, said gate providing binary information in the form of one of two different binary voltage levels at its output, and source mans having a lead for supplying binary information in the form of one of two voltage levels to the input with the gate output shifting its binary information as the source binary information on the lead shifts to maintain correlation therebetween, said interface circuit including a voltage divider having an end connected to the source means lead and another end connected to a D.C. source with an intermediate portion connected to the gate input and means for supplying a positive feedback voltage from the gate output to the gate input and in which there are means for preventing the value of the voltage at the gate input from substantially exceeding the values of voltage applied at the gate input required for the two different binary states.
Claim 3
Dependent Claim 53 words
The invention as defined in claim 1 in which the preventing means includes a fourth lead connecting a ground through a forwardly directed diode to the gate input whereby for essentially ground and negative values of the voltage of the source means lead, a slightly negative voltage is maintained on the gate input.
Claim 4
Dependent Claim 68 words
The invention as defined in claim 1 in which the gate is a non-inverting gate with correspondence between the source binary information and the gate output binary information with the voltage from the source means and the voltage from the gate output changing in the same direction and in which the positive voltage supplying means includes a resistance means connected between the gate output and the gate input.

References Cited (Backward Citations)

US3092729A Cited
US3151256A Cited
US3294981A Cited
US3305731A Cited
US3302037A Cited
US3400277A Cited
US3422282A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1976-03-26 1976-09-25 1977-03-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1980-03-26 1980-09-25 1981-03-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1984-03-26 1984-09-25 1985-03-27 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag