Parallel processing with subsampling/spreading circuitry and data transfer circuitry to and from any processing unit

Claim 2

A parallel processor comprising: two or more processing units; subsampling/spreading circuitry for receiving an item of data defining an image segment and for using the item of data to obtain another item of data that defines the same image segment with a different amount of data; data transfer circuitry connecting each of the processing units to the subsampling/spreading circuitry so that the data transfer circuitry can transfer data from any of the processing units to the subsampling/spreading circuitry and so that the data transfer circuitry can transfer data from the subsampling/spreading circuitry to any of the processing units; and control circuitry connected for providing control signals to the processing units, the data transfer circuitry, and the subsampling/spreading circuitry; the control signals causing the data transfer circuitry to transfer a first item of data obtained from the processing units to the subsampling/spreading circuitry, causing the subsampling/spreading circuitry to use the first item of data to obtain a second item of data, and causing the data transfer circuitry to transfer the second item of data to the processing units; the first item of data defining a first image segment with a first amount of data, the second item of data defining the first image segment with a second amount of data that is different than the first amount of data.

Claim 3

The parallel processor of claim I in which the subsampling/spreading circuitry comprises subsampling circuitry; the second amount of data being less than the first amount of data.

Claim 4

The parallel processor of claim 2 in which the subsampling circuitry comprises an N:1 subsampling transceiver.

Claim 5

The parallel processor of claim 3 in which N=2.

Claim 6

The parallel processor of claim 4 in which the first and second items of data each include bit sets, each bit set defining one pixel in the first image segment, the subsampling transceiver uses alternate bit sets from the first item of data to obtain the second item of data.

Claim 7

The parallel processor of claim 5 in which each bit set includes one bit.

Claim 8

The parallel processor of claim 5 in which each bit set includes a number of bits greater than one.

Claim 9

The parallel processor of claim 5 in which the control circuitry further provides control signals to the subsampling transceiver to indicate whether to use even bit sets or odd bit sets from the first item of data to obtain the second item of data.

Claim 10

The parallel processor of claim 3 in which the processing units include two or more groups, each group including N processing units; the data transfer circuitry comprising N buses, each connected for providing data to the subsampling transceiver; each group including, for each of the N buses, a respective processing unit connected to the bus such that each processing unit is connected to one of the N buses.

Claim 11

The parallel processor of claim 9 in which the first and second items of data each include bit sets, each bit set defining one pixel in the first image segment; the first item of data including a number of bit sets, the number being a multiple of N; the subsampling transceiver using one of N bit sets from the first item of data to obtain the second item of data.

Claim 12

The parallel processor of claim 10 in which the first item of data includes two or more sequences of bit sets, each sequence including N bit sets; the control circuitry further providing control signals to the subsampling transceiver to indicate one bit set in each sequence of bit sets to use in obtaining the second item of data.

Claim 13

The parallel processor of claim 9 in which the data transfer circuitry further comprises a common bus connected for receiving data from the subsampling transceiver and for providing data to any one of the N buses.

Claim 14

The parallel processor of claim 1 in which the subsampling/spreading circuitry comprises spreading circuitry; the second amount of data being greater than the first amount of data.

Claim 15

The parallel processor of claim 13 in which the spreading circuitry comprises a 1:N spreading transceiver.

Claim 16

The parallel processor of claim 14 in which N-2.

Claim 17

The parallel processor of claim 15 in which the first and second items of data each include bit sets, each bit set defining one pixel in the first image segment, the spreading transceiver using each bit set from the first item of data to obtain at least one bit set for the second item of data.

Claim 18

The parallel processor of claim 16 in which each bit set includes one bit.

Claim 19

The parallel processor of claim 16 in which each bit set includes a number of bits greater than one.

Claim 20

The parallel processor of claim 16 in which the spreading transceiver uses each bit set from the first item of data to obtain two bit sets for the second item of data.

Claim 21

The parallel processor of claim 16 in which the spreading transceiver uses each bit set from the first item of data to obtain one bit set for the second item of data; alternate bit sets of the second item of data all having equal values.

Claim 22

The parallel processor of claim 14 in which the processing units include two or more groups, each group including N processing units; the data transfer circuitry comprising N buses, each connected for receiving data from the spreading transceiver; each group including, for each of the N buses, a respective processing unit connected to the bus such that each processing unit is connected to one of the N buses.

Claim 23

The parallel processor of claim 21 in which the data transfer circuitry further comprises a common bus connected for receiving items of data from any one of the N buses and for providing items of data to the spreading transceiver.

Claim 24

The parallel processor of claim 1 in which each processing unit comprises processing circuitry for responding to instructions by performing operations on data; the control circuitry further providing a series of items of instruction data to the processing circuitry of each of the processing units; the items of instruction data indicating a sequence of instructions; the control circuitry being connected for providing each item in the series to the processing circuitry of all of the processing units in parallel.

Claim 27

The method of claim 24 in which the act of operating the subsampling/spreading circuitry obtains the second item of data so that the second amount of data is less than the first amount of data.

Claim 28

The method of claim 25 in which the second amount of data is one-half of the first amount of data.

Claim 29

The method of claim 26 in which the first and second items of data each include bit sets, each bit set defining one pixel in the first image segment, the act of operating the subsampling/spreading circuitry comprising an act of using alternate bit sets from the first item of data to obtain the second item of data.

Claim 30

The method of claim 27 in which the alternate bit sets are even numbered bit sets.

Claim 31

The method of claim 27 in which the alternate bit sets are odd numbered bit sets.

Claim 32

The method of claim 25 in which the second amount of data is (1/N) of the first amount of data.

Claim 33

The method of claim 30 in which the first and second items of data each include bit sets, each bit set defining one pixel in the first image segment; the bit sets of the first item of data including two or more sequences of bit sets, each of the sequences including N bit sets; the act of operating the subsampling/spreading circuitry comprising an act of using one bit set in each sequence of bit sets from the first item of data to obtain the second item of data.

Claim 34

The method of claim 24 in which the act of operating the subsampling/spreading circuitry obtains the second item of data so that the second amount of data is greater than the first amount of data.

Claim 35

The method of claim 32 in which the second amount of data is twice the first amount of data.

Claim 36

The method of claim 32 in which the first and second items of data each include bit sets, each bit set defining one pixel in the first image segment, the act of operating the subsampling/spreading circuitry comprising adding additional bit sets between adjacent bit sets in the first item of data to obtain the second item of data.

Claim 37

The method of claim 34 in which the additional bit sets all have a constant value.

Claim 38

The method of claim 34 in which each additional bit set has a value that is the same as the value of one of the adjacent bit sets between which the additional bit set is added.

Claim 39

The method of claim 32 in which the second amount of data is N times the first amount of data.

Claim 40

A parallel processor comprising: two or more processing units; subsampling circuitry for receiving an item of data defining an image segment and for using the item of data to obtain another item of data that defines the same image segment with less data; data transfer circuitry connecting each of the processing units to the subsampling circuitry so that the data transfer circuitry can transfer data from any of the processing units to the subsampling circuitry and so that the data transfer circuitry can transfer data from the subsampling circuitry to any of the processing units; the data transfer circuitry being connected to provide a first number of bits of data from the processing units in parallel to the subsampling circuitry and being connected to provide a second number of bits of data from the subsampling circuitry in parallel to the processing units; the first and second numbers having the ratio M/N, where N is greater than M; and control circuitry connected for providing control signals to the processing units, the data transfer circuitry, and the subsampling circuitry; the control signals causing the data transfer circuitry to transfer a first item of data obtained from the processing units to the subsampling circuitry, causing the subsampling circuitry to use the first item of data to obtain a second item of data, and causing the data transfer circuitry to transfer the second item of data to the processing units; the first item of data defining a first image segment with a first amount of data, the second item of data defining the first image segment with a second amount of data that is different than the first amount of data, the first and second amounts having the ratio M/N.

Claim 41

A parallel processor comprising: two or more processing units; subsampling circuitry for receiving an item of data defining an image segment and for using the item of data to obtain another item of data that defines the same image segment with less data; data transfer circuitry connecting each of the processing units to the subsampling circuitry so that the data transfer circuitry can transfer data from any of the processing units to the subsampling circuitry and so that the data transfer circuitry can transfer data from the subsampling circuitry to any of the processing units; the data transfer circuitry being connected to provide a first number of bits of data from the processing units in parallel to the subsampling circuitry and being connected to provide a second number of bits of data from the subsampling circuitry in parallel to the processing units; the first and second numbers having the ratio M/N, where N is greater than M; and control circuitry connected for providing control signals to the processing units, the data transfer circuitry, and the subsampling circuitry; the control signals causing the data transfer circuitry to transfer a first item of data obtained from the processing units to the subsampling circuitry, causing the subsampling circuitry to use the first item of data to obtain a second item of data, and causing the data transfer circuitry to transfer the second item of data to the processing units; the first item of data defining a first image segment with a first amount of data, the second item of data defining the first image segment with a second amount of data that is different than the first amount of data, the first and second amounts having the ratio M/N.

Claim 42

A parallel processor comprising: two or more processing units; spreading circuitry for receiving an item of data defining an image segment and for using the item of data to obtain another item of data that defines the same image segment with more data; data transfer circuitry connecting each of the processing units to the spreading circuitry so that the data transfer circuitry can transfer data from any of the processing units to the spreading circuitry and so that the data transfer circuitry can transfer data from the spreading circuitry to any of the processing units; the data transfer circuitry being connected to provide a first number of bits of data from the processing units in parallel to the spreading circuitry and being connected to provide a second number of bits of data from the spreading circuitry in parallel to the processing units; the first and second numbers having the ratio M/N, where M is greater than N; and control circuitry connected for providing control signals to the processing units, the data transfer circuitry, and the spreading circuitry; the control signals causing the data transfer circuitry to transfer a first item of data obtained from the processing units to the spreading circuitry, causing the spreading circuitry to use the first item of data to obtain a second item of data, and causing the data transfer circuitry to transfer the second item of data to the processing units; the first item of data defining a first image segment with a first amount of data, the second item of data defining the first image segment with a second amount of data that is different than the first amount of data, the first and second amounts having the ratio M/N.

Claim 43

A parallel processor comprising: two or more processing units; spreading circuitry for receiving an item of data defining an image segment and for using the item of data to obtain another item of data that defines the same image segment with more data; data transfer circuitry connecting each of the processing units to the spreading circuitry so that the data transfer circuitry can transfer data from any of the processing units to the spreading circuitry and so that the data transfer circuitry can transfer data from the spreading circuitry to any of the processing units; the data transfer circuitry being connected to provide a first number of bits of data from the processing units in parallel to the spreading circuitry and being connected to provide a second number of bits of data from the spreading circuitry in parallel to the processing units; the first and second numbers having the ratio M/N, where M is greater than N; and control circuitry connected for providing control signals to the processing units, the data transfer circuitry, and the spreading circuitry; the control signals causing the data transfer circuitry to transfer a first item of data obtained from the processing units to the spreading circuitry, causing the spreading circuitry to use the first item of data to obtain a second item of data, and causing the data transfer circuitry to transfer the second item of data to the processing units; the first item of data defining a first image segment with a first amount of data, the second item of data defining the first image segment with a second amount of data that is different than the first amount of data, the first and second amounts having the ratio M/N.

Claim 44

The parallel processor of claim 39 in which the second item of data includes additional bits in addition to bits from the first item of data, all of the additional bits having a constant value.

Claim 45

The parallel processor of claim 39 in which the second item of data includes N copied bits for each bit in the first item of data, each of the copied bits having a value that is the same as the value of the bit in the first item of data.

Claim 46

A parallel processor comprising: P groups of Q processing units, where P and Q are each greater than one; subsampling/spreading circuitry for receiving an item of data defining an image segment and for using the item of data to obtain another item of data that defines the same image segment with a different amount of data; data transfer circuitry connecting each of the processing units to the subsampling circuitry so that the data transfer circuitry can transfer data from any of the processing units to the subsampling/spreading circuitry and so that the data transfer circuitry can transfer data from the subsampling/spreading circuitry to any of the processing units; the data transfer circuitry comprising: Q buses, each connected for receiving data from and for providing data to the subsampling/spreading circuitry; each of the P groups of Q processing units including, for each of the Q buses, one processing unit connected to the bus such that each processing unit is connected for receiving data from and for providing data to one of the Q buses; and a common bus connected for receiving data from and for providing data to each of the Q buses and also connected for receiving data from and for providing data to the subsampling spreading circuitry; and control circuitry connected for providing subsampling control signals and spreading control signals to the processing units, the data transfer circuitry, and the subsampling/spreading circuitry; the subsampling control signals causing each of the Q buses to transfer an item of data obtained from one of the processing units to the subsampling/spreading circuitry, causing the subsampling/spreading circuitry to use the items of data from the Q buses to obtain a subsampled item of data, and causing the common bus to transfer the subsampled item of data to one of the Q buses for transfer to one of the processing units; the spreading control signals causing one of the Q buses to transfer one item of data from one of the processing units to the common bus for transfer to the subsampling/spreading circuitry, causing the subsampling/spreading circuitry to use the one item of data to obtain Q spread items of data, and causing each of the Q buses to transfer one of the Q spread items to one of the processing units.

Claim 47

A parallel processor comprising: P groups of Q processing units, where P and Q are each greater than one; subsampling/spreading circuitry for receiving an item of data defining an image segment and for using the item of data to obtain another item of data that defines the same image segment with a different amount of data; data transfer circuitry connecting each of the processing units to the subsampling circuitry so that the data transfer circuitry can transfer data from any of the processing units to the subsampling/spreading circuitry and so that the data transfer circuitry can transfer data from the subsampling/spreading circuitry to any of the processing units; the data transfer circuitry comprising: Q buses, each connected for receiving data from and for providing data to the subsampling/spreading circuitry; each of the P groups of Q processing units including, for each of the Q buses, one processing unit connected to the bus such that each processing unit is connected for receiving data from and for providing data to one of the Q buses; and a common bus connected for receiving data from and for providing data to each of the Q buses and also connected for receiving data from and for providing data to the subsampling spreading circuitry; and control circuitry connected for providing subsampling control signals and spreading control signals to the processing units, the data transfer circuitry, and the subsampling/spreading circuitry; the subsampling control signals causing each of the Q buses to transfer an item of data obtained from one of the processing units to the subsampling/spreading circuitry, causing the subsampling/spreading circuitry to use the items of data from the Q buses to obtain a subsampled item of data, and causing the common bus to transfer the subsampled item of data to one of the Q buses for transfer to one of the processing units; the spreading control signals causing one of the Q buses to transfer one item of data from one of the processing units to the common bus for transfer to the subsampling/spreading circuitry, causing the subsampling/spreading circuitry to use the one item of data to obtain Q spread items of data, and causing each of the Q buses to transfer one of the Q spread items to one of the processing units.