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EP0431961A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Image reduction/enlargement technique

Assignee: Xerox Corp
•
Filing: 1990-12-07
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Granted: —
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Expires: 2010-12-07
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Abstract

Abstract A method of reducing an M X N input binary image (M rows of N pixels each) by a factor of m vertically and n horizontally includes the steps of performing at least one logical operation between bits in consecutive groups of m adjacent rows to provide a resultant single row for each group of m rows, and performing at least adjacent columns to provide a resultant single column for each groups of n columns. For certain types of reductions the resulting reduced image will be the desired output image, while for other types, the resultant image will be one of a required plurality of intermediate images, which are then combined to provide the desired output image.

Inventors

  • 👤 Dan S. Bloomberg
  • 👤 Daniel Davies

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-11-01 15:48
CPC Classifications
G; G06; G06T; G06T3/00; G06T3/40; G06T3/4023

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 99 words
A method of reducing a binary image for further processing, wherein the image is divided into subregions, each having m pixels down and n pixels across, each to be mapped to a single pixel in the reduced image, comprising the steps of: performing at least one logical operation between bits in consecutive groups of m adjacent rows to provide a resultant row for each group of m rows (Fig. 2A); and performing at least one logical operation between bits in consecutive groups of n adjacent columns to provide a resultant column for each group of n columns (Fig 2B).
Claim 2
Dependent Claim 57 words
A method as claimed in claim 1 for performing a 2 × 2 reduction with a threshold of 1 on a binary image, wherein the logical operations comprise: logically ORing pairs of adjacent rows to provide a reduced number of rows; and logically ORing pairs of adjacent columns to provide a reduced number of columns (Fig 2C)
Claim 3
Dependent Claim 144 words
A method as claimed in claim 1 for performing a 2 × 2 reduction with a threshold of 2 on a binary image, wherein the logical operations comprise: logically ORing pairs of adjacent rows in the original binary image to provide a first intermediate image having a reduced number of rows logically ANDing pairs of adjacent columns in the first intermediate image to provide a second intermediate image having a reduced number of rows and columns; logically ANDing pairs of adjacent rows in the original image to provide a third intermediate image having a reduced number of rows; logically ORing pairs of adjacent columns in the third intermediate image to provide a fourth intermediate image having a reduced number of rows and columns; and logically ORing the second and fourth intermediate images to provide the reduced image with a threshold of 2 (Fig. 2C).
Claim 4
Dependent Claim 144 words
A method as claimed in claim 1 for performing a 2 × 2 reduction with a threshold of 3 on a binary image, wherein the logical operations comprise: logically ORing pairs of adjacent rows in the original binary image to provide a first intermediate image having a reduced number of rows; logically ANDing pairs of adjacent columns in the first intermediate image to provide a second intermediate image having a reduced number of rows and columns; logically ANDing pairs of adjacent rows in the original image to provide a third intermediate image having a reduced number of rows; logically ORing pairs of adjacent columns in the third intermediate image to provide a fourth intermediate image having a reduced number of rows and columns; and logically ANDing the second and fourth intermediate images to provide the reduced image with a threshold of 3 (Fig. 2C).
Claim 5
Dependent Claim 57 words
A method as claimed in claim 1 for performing a 2 × 2 reduction with a threshold of 4 on a binary image, wherein the logical operations comprise: logically ANDing pairs of adjacent rows to provide a reduced number of rows; and logically ANDing pairs of adjacent columns to provide a reduced number of columns (Fig 2C).
Claim 6
Independent Claim 231 words
A method of performing a given logical operation between groups of n adjacent columns in a binary source image to provide a destination image having 1/n times as many columns, wherein each row of pixels in the source image is stored as a logically contiguous source pixelword and each row of pixels in the destination image is stored as a logically contiguous destination pixelword which is 1/n as long as the source pixelword, comprising the steps of: providing a lookup table memory having 2 n*k locations, each location being sized to hold a k-bit entry, where n and k are non-zero integers, each location being addressable by an (n*k)-bit address, address bits being designated (0) to (n*k - 1); storing in each location a k-bit entry, entry bits being designated 0 to (k - 1), entry bit (i) being derived from the given logical combination of address bit (n*k) through address bit (n*i + n - 1); accessing each source pixelword in the source image, an (n*k)-bit source pixelword segment at a time; and for each (n*k)-bit source pixelword segment thus accessed, accessing the entry in the lookup table memory that is stored in the location whose (n*k)-bit address corresponds to the value of the (n*k)-bit source pixelword segment, and storing the k-bit entry value as a k-bit destination pixelword segment in the destination pixelword that corresponds to the source pixelword.
Claim 7
Independent Claim 225 words
A method of expanding a binary source image to provide a destination image having n times as many columns, wherein each row of pixels in the source image is stored as a logically contiguous source pixelword and each row of pixels in the destination image is stored as a logically contiguous destination pixelword which is n times as long as the source pixelword, comprising the steps of: providing a lookup table memory having 2 k locations, each location being sized to hold a, n*k-bit entry, where n and k are non-zero integers, each location being addressable by a k-bit address, address bits being designated (0) to (k - 1); storing in each location an n*k-bit entry, entry bits being designated (0) to (n*k - 1), entry bits (n*i) through (n*i + n - 1) each having the same value as address bit (i) for i = 0 through (k - 1) accessing each source pixelword in the source image, a k-bit source pixelword segment at a time; and for each k-bit source pixelword segment thus accessed, accessing the entry in the lookup table memory that is stored in the location whose k-bit address corresponds to the value of the k-bit source pixelword segment, and storing the n*k-bit entry value as an n*k-bit destination pixelword segment in the destination pixelword that corresponds to the source pixelword.
Claim 8
Dependent Claim 110 words
Apparatus comprising: means (210) for combining a 2Q-bit pixelword with a version of the pixelword that is shifted by one bit and providing the result at a 2Q-bit data port; first and second Q-bit latched transceivers (220, 222), each having first and second Q-bit ports (220a, b; 222a, b); the first ports of said first and second transceivers each being coupled to the same set of alternating bit positions of said data port; said second port of said first transceiver being coupled to bits (0) through (Q - 1) of said data port; and said second port of said second transceiver being coupled to bits (Q) through (2Q - 1).
Claim 9
Dependent Claim 49 words
Apparatus as claimed in claim 8, wherein the said means comprises: a 2Q-bit data port having bit positions designated (0) through (2Q - 1); a first 2Q-bit register; and a second 2Q-bit register, being a shift register; each of said registers being selectively bidirectionally coupled to said data port.
Claim 10
Dependent Claim 38 words
Apparatus as claimed in claim 9, and further comprising means for establishing each bit position of said data port at a logical true level when neither of said transceivers nor said data port is driving that bit position.

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