Patent US5436559A successfully refreshed from Google Patents.
US5436559A
Expired / Lapsed
US
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Method for testing semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 1993-08-23
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Granted: 1995-07-25
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Expires: 2013-08-23
Abstract
Abstract A method of testing a semiconductor device operating according to predetermined testing information. An output signal of the semiconductor device is received through a signal transmission line and a reference voltage is generated in accordance with an expected logical level of the output signal. The reference voltage is compared with a voltage of the output signal thus received and a current flow is supplied to the signal transmission line in accordance with the result. A logical level of the output signal thus received is determined and a decision is made whether the semiconductor device operates correctly.
Inventors
- 👤 Ryoichi Takagi
- 👤 Tetsuo Tada
- 👤 Koji Tanaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:07
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2832; G01R31/2836; G01R31/2844; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31924; G01R31/3193; G01R31/31937
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
107 words
A method of testing a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device through a signal transmission line; generating a reference voltage in accordance with an expected logical level of said output signal; comparing said reference voltage and a voltage of the output signal thus received; supplying a current flow to said signal transmission line in accordance with the result in said step of comparing; and determining a logical level of said output signal thus received; and deciding whether the semiconductor device operates correctly according to the result of determination in said step of determining.
Claim 2
Independent Claim
107 words
A method of testing a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device through a signal transmission line; generating a reference voltage in accordance with an expected logical level of said output signal; comparing said reference voltage and a voltage of the output signal thus received; supplying a current flow to said signal transmission line in accordance with the result in said step of comparing; and determining a logical level of said output signal thus received; and deciding whether the semiconductor device operates correctly according to the result of determination in said step of determining.
Claim 3
Dependent Claim
86 words
A method of testing a semiconductor device according to claim 1, wherein said expected logical level includes a first logical level and a second logical level, and wherein said step of generating includes the steps of generating a first reference voltage corresponding to said first logical level when said expected logical level of the output indicates said first logical level, and generating a second reference voltage corresponding to said second logical level when said expected logical level of the output signal indicates said second logical level.
Claim 4
Dependent Claim
73 words
A method of testing a semiconductor device according to claim 1, wherein said expected logical level includes a first logical level and a second logical level, and wherein said step of supplying includes the steps of injecting said current flow to said transmission line where said expected logical level indicates the first logical level, and extracting said current flow from said transmission line where said expected logical level indicates the second logical level.
Claim 5
Independent Claim
161 words
A method of testing a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device at an input node through a signal transmission line; coupling a current flow source to said signal transmission line where there is a possibility of occurrence of an undershooting on said signal transmission line at said input node, in accordance with an expected logical level of the output signal; coupling a current flow sink to said transmission line at said input node where there is a possibility of occurrence of an overshooting on said transmission line at said input node, in accordance with the expected logical level of the output signal; determining a logical level of the output signal received at input node, after substantially stabilizing a potential level of the output signal at said input node; and deciding whether said semiconductor device operates correctly according to the result of determination in said step of determining.
Claim 6
Independent Claim
161 words
A method of testing a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device at an input node through a signal transmission line; coupling a current flow source to said signal transmission line where there is a possibility of occurrence of an undershooting on said signal transmission line at said input node, in accordance with an expected logical level of the output signal; coupling a current flow sink to said transmission line at said input node where there is a possibility of occurrence of an overshooting on said transmission line at said input node, in accordance with the expected logical level of the output signal; determining a logical level of the output signal received at input node, after substantially stabilizing a potential level of the output signal at said input node; and deciding whether said semiconductor device operates correctly according to the result of determination in said step of determining.
Claim 7
Dependent Claim
222 words
In an apparatus for testing normal operation of a semiconductor device including a pin electronics circuit having an input node and a signal transmission line connecting said input node to said semiconductor device, a method of reducing undershooting or overshooting on said signal transmission line at said input node during testing of said semiconductor device when an impedance of said signal transmission line is higher than an output impedance of said semiconductor device, comprising the steps of: receiving an output signal of said semiconductor device at said input via said signal transmission line; generating a reference voltage in accordance with an expected logical level of said output signal; comparing said reference voltage and a voltage of the output signal thus received; supplying a first current flow to said signal transmission line at said input node in accordance with the result in said step of comparing to reduce undershooting on said signal transmission line at said input node; supplying a second current flow to said signal transmission line at said input node in accordance with the result in said step of comparing to reduce overshooting on said signal transmission line at said input node; and determining the logical level of said output signal thus received at said input node after substantially stabilizing a potential level of the output signal at said input node.
Claim 8
Dependent Claim
222 words
In an apparatus for testing normal operation of a semiconductor device including a pin electronics circuit having an input node and a signal transmission line connecting said input node to said semiconductor device, a method of reducing undershooting or overshooting on said signal transmission line at said input node during testing of said semiconductor device when an impedance of said signal transmission line is higher than an output impedance of said semiconductor device, comprising the steps of: receiving an output signal of said semiconductor device at said input via said signal transmission line; generating a reference voltage in accordance with an expected logical level of said output signal; comparing said reference voltage and a voltage of the output signal thus received; supplying a first current flow to said signal transmission line at said input node in accordance with the result in said step of comparing to reduce undershooting on said signal transmission line at said input node; supplying a second current flow to said signal transmission line at said input node in accordance with the result in said step of comparing to reduce overshooting on said signal transmission line at said input node; and determining the logical level of said output signal thus received at said input node after substantially stabilizing a potential level of the output signal at said input node.
Claim 9
Dependent Claim
91 words
A method of reducing generation of undershoot or overshoot according to claim 5, wherein said expected logical level includes a first logical level and a second logical level, and wherein said step of generating a reference voltage includes the steps of generating a first reference voltage corresponding to said first logical level when said expected logical level of the output indicates said first logical level, and generating a second reference voltage corresponding to said second logical level when said expected logical level of the output signal indicates said second logical level.
Claim 10
Dependent Claim
75 words
A method of reducing generation of undershoot or overshoot according to claim 5, wherein said expected logical level includes a first logical level and a second logical level, and wherein said step of supplying includes the steps of injecting said current flow to said transmission line where said expected logical level indicates the first logical level, and extracting said current flow from said transmission line where said expected logical level indicates the second logical level.
Claim 11
Dependent Claim
209 words
In an apparatus for testing normal operation of a semiconductor device including a pin electronics circuit having an input node and a signal transmission line connecting said input node to said semiconductor device, a method of reducing undershooting or overshooting on said signal transmission line at said input node during testing of said semiconductor device when an impedance of said signal transmission line is higher than an output impedance of said semiconductor device, comprising the steps of: receiving an output signal of said semiconductor device at said input via said signal transmission line; coupling a current flow source to said signal transmission line at said input node where there is a possibility of occurrence of an undershooting on said signal transmission line at said input node, in accordance with an expected logical level of the output signal; coupling a current flow sink to said signal transmission line at said input node where there is a possibility of occurrence of an overshooting on said signal transmission line at said input node, in accordance with an expected logical level of the output signal; and determining a logical level of the output signal received at said input node, after substantially stabilizing a potential level of the output signal at said input node.
Claim 12
Dependent Claim
209 words
In an apparatus for testing normal operation of a semiconductor device including a pin electronics circuit having an input node and a signal transmission line connecting said input node to said semiconductor device, a method of reducing undershooting or overshooting on said signal transmission line at said input node during testing of said semiconductor device when an impedance of said signal transmission line is higher than an output impedance of said semiconductor device, comprising the steps of: receiving an output signal of said semiconductor device at said input via said signal transmission line; coupling a current flow source to said signal transmission line at said input node where there is a possibility of occurrence of an undershooting on said signal transmission line at said input node, in accordance with an expected logical level of the output signal; coupling a current flow sink to said signal transmission line at said input node where there is a possibility of occurrence of an overshooting on said signal transmission line at said input node, in accordance with an expected logical level of the output signal; and determining a logical level of the output signal received at said input node, after substantially stabilizing a potential level of the output signal at said input node.
Claim 13
Independent Claim
97 words
A method of determining a logical level of an output signal of a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device through a signal transmission line; generating a reference voltage in accordance with an expected logical level of said output signal; comparing said reference voltage and a voltage of the output signal thus received; and supplying a current flow to said signal transmission line in accordance with the result in said step of comparing; and determining a logical level of said output signal thus received.
Claim 14
Independent Claim
97 words
A method of determining a logical level of an output signal of a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device through a signal transmission line; generating a reference voltage in accordance with an expected logical level of said output signal; comparing said reference voltage and a voltage of the output signal thus received; and supplying a current flow to said signal transmission line in accordance with the result in said step of comparing; and determining a logical level of said output signal thus received.
Claim 15
Independent Claim
151 words
A method of determining a logical level of an output signal of a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device at an input node through a signal transmission line; coupling a current flow source to said transmission line where there is a possibility of occurrence of an undershooting on said transmission line at said input node, in accordance with an expected logical level of the output signal; coupling a current flow sink to said signal transmission line at said input node where there is a possibility of occurrence of an overshooting on said signal transmission line at said input node, in accordance with the expected logical level of the output signal; and determining a logical level of the output signal received at input node, after substantially stabilizing a potential level of the output signal at said input node.
Claim 16
Independent Claim
151 words
A method of determining a logical level of an output signal of a semiconductor device operating according to predetermined testing information, comprising the steps of: receiving an output signal of said semiconductor device at an input node through a signal transmission line; coupling a current flow source to said transmission line where there is a possibility of occurrence of an undershooting on said transmission line at said input node, in accordance with an expected logical level of the output signal; coupling a current flow sink to said signal transmission line at said input node where there is a possibility of occurrence of an overshooting on said signal transmission line at said input node, in accordance with the expected logical level of the output signal; and determining a logical level of the output signal received at input node, after substantially stabilizing a potential level of the output signal at said input node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-24 | 1999-01-23 | 1999-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-24 | 2003-01-23 | 2003-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-24 | 2007-01-23 | 2007-07-25 | $7700.00 | Window Closed / Lapsed |