US4110698A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital waveform conditioning circuit
Assignee: Individual
•
Filing: 1977-01-21
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Granted: 1978-08-29
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Expires: 1997-01-21
Abstract
Abstract A digital waveform conditioning circuit includes a noninverting amplifier stage. A source of digital information is coupled to the input of the amplifier via a series resistor. The amplifier output is coupled to a digital utilization circuit. A feedback capacitor is coupled between the amplifier input and output terminals to provide integration of unwanted input noise pulses, positive feedback during threshold transitions for fast rise and fall times, and a hold-off voltage for a specified time thereafter to prevent oscillations during said transitions.
Inventors
- 👤 Adelore F. Petrie
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:57
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/125; H03K5/1252
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
178 words
A digital waveform conditioning circuit for removing extraneous noise and switching transients for use in a digital electronic system in which information is conveyed as signals having predetermined logic states, said signals being subjected to extraneous noise and switching transients which tend to produce undesired reactions within said system, said circuit comprising: signal buffer amplifier means having a gain of more than one, responsive to applied signals, producing output signals having the same polarity as the applied signals, said signal buffer amplifier means including a noninverting buffer amplifier having an input terminal and an output terminal; and feedback means, coupled to said signal buffer amplifier means, combining the functions of integrating said applied signals and adding a portion of said output signal to said applied signals, said feedback means including a capacitor coupled between said input and output terminals, said feedback means including a series resistor coupling said input terminal to said information system; whereby said amplifier means is operating in the switching mode with said feedback means ensuring abrupt changes between logic states in said output signals.
Claim 2
Dependent Claim
178 words
A digital waveform conditioning circuit for removing extraneous noise and switching transients for use in a digital electronic system in which information is conveyed as signals having predetermined logic states, said signals being subjected to extraneous noise and switching transients which tend to produce undesired reactions within said system, said circuit comprising: signal buffer amplifier means having a gain of more than one, responsive to applied signals, producing output signals having the same polarity as the applied signals, said signal buffer amplifier means including a noninverting buffer amplifier having an input terminal and an output terminal; and feedback means, coupled to said signal buffer amplifier means, combining the functions of integrating said applied signals and adding a portion of said output signal to said applied signals, said feedback means including a capacitor coupled between said input and output terminals, said feedback means including a series resistor coupling said input terminal to said information system; whereby said amplifier means is operating in the switching mode with said feedback means ensuring abrupt changes between logic states in said output signals.
Claim 3
Dependent Claim
28 words
The digital waveform conditioning circuit set forth in claim 1 further including a current limiting resistor connected between said capacitor and the input terminal of said buffer amplifier.
Claim 4
Dependent Claim
29 words
The digital waveform conditioning circuit set forth in claim 2 further including a shunt resistor coupled between said input and output terminals for inhibiting the production of oscillatory signals.
Claim 5
Dependent Claim
29 words
The digital waveform conditioning circuit set forth in claim 1 further including a shunt resistor coupled between said input and output terminals for inhibiting the production of oscillatory signals.
References Cited (Backward Citations)
US3588531A
Cited
US3802747A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |