US5436503A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method of manufacturing the same
Assignee: Panasonic Holdings Corp
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Filing: 1993-11-17
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Granted: 1995-07-25
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Expires: 2013-11-17
Abstract
Abstract The top surface of an insulating substrate is formed with a plurality of electrodes for bump connection, while the undersurface of the insulating substrate is formed with external terminals which are arranged in an array. On the insulating substrate is provided a semiconductor chip. The undersurface of the semiconductor chip is formed with bump electrodes. The electrodes for bump connection are electrically connected to the bump electrodes by means of a conductive adhesive. The space between the semiconductor chip and the insulating substrate is filled with a resin which integrates the above two and dissipates heat generated from the semiconductor chip.
Inventors
- 👤 Yoshinobu Kunitomo
- 👤 Makoto Nozu
- 👤 Yasuyuki Sakashita
- 👤 Masahide Tsukamoto
- 👤 Seiichi Nakatani
- 👤 Keiji Saeki
- 👤 Yoshifumi Kitayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:59
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W74/40; H10W74/47; H10W74/473; H10W70/682; H10W70/685; H10W72/00; H10W72/01; H10W72/012; H10W72/01221; H10W72/01225; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/073; H10W72/07331; H10W72/075; H10W72/20; H10W72/251; H10W72/252; H10W72/29; H10W72/30; H10W72/321; H10W72/325; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/59; H10W72/851; H10W72/853; H10W72/856; H10W72/874; H10W72/884; H10W72/90; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
154 words
A semiconductor device comprising: an insulating substrate provided with a plurality of electrodes for bump connection on its top surface and with external terminals arranged in an array on its undersurface; a semiconductor chip provided above said insulating substrate and having bump electrodes formed on its undersurface so that the bump electrodes are electrically connected to said electrodes for bump connection by means of a conductive adhesive; a resin which fills the space between said semiconductor chip and said insulating substrate so as to integrate said semiconductor chip and said insulating substrate, said resin dissipating heat generated from said semiconductor chip; a conductive layer formed on the top surface of said semiconductor chip; an electrode for back bias formed on the top surface of said insulating substrate; and a conductive film formed on the circumferential side face of said resin so as to electrically connect said conductive layer and said electrode for back bias.
Claim 2
Dependent Claim
154 words
A semiconductor device comprising: an insulating substrate provided with a plurality of electrodes for bump connection on its top surface and with external terminals arranged in an array on its undersurface; a semiconductor chip provided above said insulating substrate and having bump electrodes formed on its undersurface so that the bump electrodes are electrically connected to said electrodes for bump connection by means of a conductive adhesive; a resin which fills the space between said semiconductor chip and said insulating substrate so as to integrate said semiconductor chip and said insulating substrate, said resin dissipating heat generated from said semiconductor chip; a conductive layer formed on the top surface of said semiconductor chip; an electrode for back bias formed on the top surface of said insulating substrate; and a conductive film formed on the circumferential side face of said resin so as to electrically connect said conductive layer and said electrode for back bias.
Claim 3
Dependent Claim
52 words
A semiconductor device according to claim 1, wherein the angle formed between the circumferential side face of said resin and the top surface of said insulating substrate is 60° or less and said conductive film is composed of a conductive ink with which the circumferential side face of said resin is printed.
References Cited (Backward Citations)
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JPS62136865A
Cited
JPS63313846A
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US5001542A
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US5128746A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-24 | 1999-01-23 | 1999-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-24 | 2003-01-23 | 2003-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-24 | 2007-01-23 | 2007-07-25 | $7700.00 | Window Closed / Lapsed |