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US5436478A
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Fast access AMG EPROM with segment select transistors which have an increased width
Assignee: National Semiconductor Corp
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Filing: 1994-03-16
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Granted: 1995-07-25
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Expires: 2014-03-16
Abstract
Abstract The current driven by the segment select transistors of an alternate-metal, virtual-ground (AMG) electrically programmable read-only-memory (EPROM), is increased by eliminating the even numbered segment select transistors in every other row of segment select transistors, and the odd numbered segment select transistors in the remaining rows, and by changing the current path through the segment so that the current flows from a segment select transistor in one row of segment select transistors to a segment select transistor in an adjacent row of transistors. By eliminating every other segment select transistor in each row of transistors, the maximum pitch of the segment select transistors can be substantially increased, thereby providing the required programming current, while at the same time maintaining the required isolation between adjacent segment select transistors.
Inventors
- 👤 Albert M. Bergemont
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:33
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0491; H; H10; H10B; H10B41/00; H10B41/30; H10B69/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
299 words
A segment of an electrically programmable read-only-memory (EPROM) formed in a semiconductor substrate, the segment comprising: a plurality of spaced-apart, parallel, bit lines formed in the semiconductor substrate so that each bit line extends from a first side of the segment to a second side of the segment; a plurality of spaced-apart memory cells formed in a plurality of rows so that one memory cell in each row of memory cells is formed on the substrate between each pair of adjacent bit lines; a plurality of word lines formed so that each word line contacts each memory cell in a row of memory cells; a plurality of spaced-apart access select transistors formed in a plurality of pairs of rows so that, in each row of access select transistors, one access select transistor is formed on the substrate between every other pair of bit lines, and so that, in each pair of rows of access select transistors, one access select transistor is formed between each pair of bit lines; and a plurality of access select lines formed so that each access select line contacts each of the access select transistors in a row of access select transistors; and a plurality of segment select transistors formed so that only every fourth bit line of the bit lines at the first side of the segment is connected to a segment select transistors, and so that only every fourth bit line of the bit lines at the second side of the segment is connected to a segment select transistor, the segment select transistors connected to the bit lines at the first side being staggered with respect to the segment select transistors connected to the bit lines at the second side so that every other bit line is contacted by one segment select transistor.
Claim 2
Dependent Claim
299 words
A segment of an electrically programmable read-only-memory (EPROM) formed in a semiconductor substrate, the segment comprising: a plurality of spaced-apart, parallel, bit lines formed in the semiconductor substrate so that each bit line extends from a first side of the segment to a second side of the segment; a plurality of spaced-apart memory cells formed in a plurality of rows so that one memory cell in each row of memory cells is formed on the substrate between each pair of adjacent bit lines; a plurality of word lines formed so that each word line contacts each memory cell in a row of memory cells; a plurality of spaced-apart access select transistors formed in a plurality of pairs of rows so that, in each row of access select transistors, one access select transistor is formed on the substrate between every other pair of bit lines, and so that, in each pair of rows of access select transistors, one access select transistor is formed between each pair of bit lines; and a plurality of access select lines formed so that each access select line contacts each of the access select transistors in a row of access select transistors; and a plurality of segment select transistors formed so that only every fourth bit line of the bit lines at the first side of the segment is connected to a segment select transistors, and so that only every fourth bit line of the bit lines at the second side of the segment is connected to a segment select transistor, the segment select transistors connected to the bit lines at the first side being staggered with respect to the segment select transistors connected to the bit lines at the second side so that every other bit line is contacted by one segment select transistor.
Claim 3
Dependent Claim
57 words
The segment of claim 1 and further comprising a plurality of segment limes formed so that a first segment line contacts each of the segment select transistors connected to the bit lines at the first side, and a second segment line contacts each of the segment select transistors connected to the bit lines at the second side.
Claim 4
Dependent Claim
22 words
The segment of claim 1 wherein every other bit line of the plurality of bit lines comprises a graded N+/N- bit line.
Claim 5
Independent Claim
558 words
A method for programming a selected cell in a segment of an electrically programmable read-only memory formed in a semiconductor substrate, the method comprising the steps of: providing the electrically programmable read-only-memory (EPROM), the EPROM comprising: a plurality of spaced-apart, parallel, bit lines formed in the semiconductor substrate so that each bit line extends from a first side of the segment to a second side of the segment, a plurality of spaced-apart memory cells formed in a plurality of rows so that one memory cell in each row of memory cells is formed on the substrate between each pair of adjacent bit lines, a plurality of word lines formed so that each word line contacts each memory cell in a row of memory cells, one word line corresponding to the selected cell, a plurality of spaced-apart access select transistors formed in a plurality of pairs of rows so that, in each row of access select transistors, one access select transistor is formed on the substrate between every other pair of bit lines, and so that, in each pair of rows of access select transistors, one access transistor is formed between each pair of bit lines, a plurality of access select lines formed so that each access select line contacts each of the access select transistors in a row of access select transistors, two pair of access select lines of the plurality of access select lines corresponding to the selected cell, said two pair of access select lines including a first pair of access select lines and a second pair of access select lines; a plurality of segment select transistors formed so that only every fourth bit line of the bit lines at the first side of the segment is connected to a segment select transistor, and so that only every fourth bit line of the bit lines at the second side of the segment is connected to a segment select transistor, the segment select transistors connected to the bit lines at the first side being staggered with respect to the segment select transistors connected to the bit lines at the second side so that every other bit line is contacted by one segment select transistor, a plurality of segment lines formed so that a first segment line contacts each of the segment select transistors connected to the bit lines at the first side, a second segment line contacts each of the segment select transistors at the second side, one segment select transistor in the first segment line corresponds to the selected cell, and one segment select transistor in the second segment line corresponds to the selected cell, setting the first and second segment lines to a programming voltage; setting one access select line of the first pair of access select lines, and one access select line of the second pair of access select lines to a supply voltage; setting a remaining access select line of the first pair of access select lines, and a remaining access select line of the second pair of access select lines to ground; setting said one word line to the programming voltage; setting the bit line than contacts said one segment select transistor in the first segment line to a first voltage; and setting the bit line that contacts said one segment select transistor in the second segment line to a second voltage.
Claim 6
Independent Claim
558 words
A method for programming a selected cell in a segment of an electrically programmable read-only memory formed in a semiconductor substrate, the method comprising the steps of: providing the electrically programmable read-only-memory (EPROM), the EPROM comprising: a plurality of spaced-apart, parallel, bit lines formed in the semiconductor substrate so that each bit line extends from a first side of the segment to a second side of the segment, a plurality of spaced-apart memory cells formed in a plurality of rows so that one memory cell in each row of memory cells is formed on the substrate between each pair of adjacent bit lines, a plurality of word lines formed so that each word line contacts each memory cell in a row of memory cells, one word line corresponding to the selected cell, a plurality of spaced-apart access select transistors formed in a plurality of pairs of rows so that, in each row of access select transistors, one access select transistor is formed on the substrate between every other pair of bit lines, and so that, in each pair of rows of access select transistors, one access transistor is formed between each pair of bit lines, a plurality of access select lines formed so that each access select line contacts each of the access select transistors in a row of access select transistors, two pair of access select lines of the plurality of access select lines corresponding to the selected cell, said two pair of access select lines including a first pair of access select lines and a second pair of access select lines; a plurality of segment select transistors formed so that only every fourth bit line of the bit lines at the first side of the segment is connected to a segment select transistor, and so that only every fourth bit line of the bit lines at the second side of the segment is connected to a segment select transistor, the segment select transistors connected to the bit lines at the first side being staggered with respect to the segment select transistors connected to the bit lines at the second side so that every other bit line is contacted by one segment select transistor, a plurality of segment lines formed so that a first segment line contacts each of the segment select transistors connected to the bit lines at the first side, a second segment line contacts each of the segment select transistors at the second side, one segment select transistor in the first segment line corresponds to the selected cell, and one segment select transistor in the second segment line corresponds to the selected cell, setting the first and second segment lines to a programming voltage; setting one access select line of the first pair of access select lines, and one access select line of the second pair of access select lines to a supply voltage; setting a remaining access select line of the first pair of access select lines, and a remaining access select line of the second pair of access select lines to ground; setting said one word line to the programming voltage; setting the bit line than contacts said one segment select transistor in the first segment line to a first voltage; and setting the bit line that contacts said one segment select transistor in the second segment line to a second voltage.
References Cited (Backward Citations)
US5246874A
Cited
US5315541A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-07-24 | 1999-01-23 | 1999-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-24 | 2003-01-23 | 2003-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-24 | 2007-01-23 | 2007-07-25 | $7700.00 | Window Closed / Lapsed |