Patent US5434993A successfully refreshed from Google Patents.
US5434993A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories
Assignee: Xerox Corp
•
Filing: 1992-11-09
•
Granted: 1995-07-18
•
Expires: 2012-11-09
Abstract
Abstract A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has an associated cache control system. When a processor's cache control system does not have a required memory location in the cache memory, it broadcasts a memory request packet across the memory bus for the required data. If an owned cache line is being replaced, the cache control system copies the old cache line data to the pending write-back cache controller which is responsible for the write-backs of owned cache lines to main memory. The cache control system then transfers ownership of the old replaced cache line to the pending write-back controller. When the cache control system receives the new cache line information from the memory bus, it immediately replaces the cache line and allows the processing to continue. By buffering the old cache line in the pending write-back controller, the cache control system allows the new cache line to be requested before the old cache line is written back to main memory thereby reducing the cache line replacement latency period.
Inventors
- 👤 Bjorn Liencres
- 👤 Douglas Lee
- 👤 Pradeep S. Sindhu
- 👤 Tung Pham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:13
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0806; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
294 words
A computer system including a first processor subsystem and a main memory, said first processor subsystem and main memory coupled via a packet-switched memory bus, said first processor subsystem having a write-back cache memory system, said write-back cache memory system comprising: a cache memory, said cache memory comprising more than one cache line, each of said cache lines storing information; a cache directory, said cache directory describing said information stored in said cache memory, said cache directory comprising an address tag and a plurality of status bits for each cache line in said cache memory, said plurality of status bits including a valid bit and an owned bit; a cache control system, said cache control system coupled to said cache memory and said cache directory, said cache control system further coupled to said packet-switched memory bus, said cache control system maintaining said cache directory; a pending write-back controller, said pending write-back controller coupled to said cache control system, said pending write-back controller comprising; a data memory for buffering a plurality of owned cache lines, each of said owned cache lines having a corresponding main memory address; a write-back address tag and a plurality of status bits for each of said plurality of owned cache lines stored in the data memory, said write-back address tag defining a main memory address of said owned cache line; a write-back memory, said write-back memory storing an encoded list of owned cache lines stored in said data memory which must be written back to said main memory; and a pending write-back control logic unit for controlling said pending write-back controller such that each owned cache line listed in said encoded list in said write-back memory is written back to said main memory after each owned cache line is replaced.
Claim 2
Dependent Claim
294 words
A computer system including a first processor subsystem and a main memory, said first processor subsystem and main memory coupled via a packet-switched memory bus, said first processor subsystem having a write-back cache memory system, said write-back cache memory system comprising: a cache memory, said cache memory comprising more than one cache line, each of said cache lines storing information; a cache directory, said cache directory describing said information stored in said cache memory, said cache directory comprising an address tag and a plurality of status bits for each cache line in said cache memory, said plurality of status bits including a valid bit and an owned bit; a cache control system, said cache control system coupled to said cache memory and said cache directory, said cache control system further coupled to said packet-switched memory bus, said cache control system maintaining said cache directory; a pending write-back controller, said pending write-back controller coupled to said cache control system, said pending write-back controller comprising; a data memory for buffering a plurality of owned cache lines, each of said owned cache lines having a corresponding main memory address; a write-back address tag and a plurality of status bits for each of said plurality of owned cache lines stored in the data memory, said write-back address tag defining a main memory address of said owned cache line; a write-back memory, said write-back memory storing an encoded list of owned cache lines stored in said data memory which must be written back to said main memory; and a pending write-back control logic unit for controlling said pending write-back controller such that each owned cache line listed in said encoded list in said write-back memory is written back to said main memory after each owned cache line is replaced.
Claim 3
Dependent Claim
85 words
The computer system including write-back cache memory system as claimed in claim 1 wherein said pending write-back controller further comprises: a read request memory, said read request memory storing a list of read requests received from a second processor subsystem coupled to said packet-switched memory bus, said read requests requesting the owned cache lines in said data memory; and said pending write-back control logic unit sending a read request reply to said second processor subsystem for each read request stored in said read request memory.
Claim 4
Dependent Claim
29 words
The write-back cache memory system as claimed in claim 2 wherein said plurality of status bits in said pending write-back controller comprise a valid bit and an owned bit.
Claim 5
Dependent Claim
70 words
The write-back cache memory system as claimed in claim 3 wherein said pending write-back control logic unit further comprises means for resetting the owned status bit for an owned cache line stored in said data memory when a write transaction occurs on said packet-switched memory bus to the corresponding main memory address of the owned cache line such that said pending write-back controller does not write-back said owned cache line.
Claim 6
Dependent Claim
26 words
The write-back cache memory system as claimed in claim 4 wherein said write-back memory in said pending write-back control logic unit comprises a first-in-first-out (FIFO) memory.
Claim 7
Dependent Claim
27 words
The write-back cache memory system as claimed in claim 5 wherein said read request memory in said pending write-back control logic unit comprises a first-in-first-out (FIFO) memory.
Claim 8
Dependent Claim
92 words
The write-back cache memory system as claimed in claim 6 wherein said cache control system comprises: a bus cache controller, said bus cache controller interfacing said cache control system to the packet-switched memory bus, said bus cache controller having a first cache directory; a processor cache controller, said processor cache controller interfacing said cache memory to a first processor in said first processor subsystem, said processor cache controller having a second cache directory; and a packet-switched cache bus, said packet-switched cache bus coupling said bus cache controller and said processor cache controller.
Claim 9
Dependent Claim
43 words
The write-back cache memory system as claimed in claim 7 wherein each of said cache lines are further subdivided into M subblocks, each of said subblocks having separate status bits, each of said subblocks of said cache lines handled as individual memory blocks.
Claim 10
Dependent Claim
294 words
In a computer system including first processor subsystem and a main memory, said first processor subsystem and main memory coupled via a packet-switched memory bus, a write-back cache memory system in said first processor subsystem, said write-back cache memory system comprising: a cache memory, said cache memory comprising more than one cache line, each of said cache lines storing lines of information, each of said lines of information having a corresponding main memory address; a cache directory, said cache directory storing an address tag and a set of status bits for each cache line in said cache memory, said address tag being the corresponding main memory address for said cache line; a write-back cache control system, said write-back cache control system maintaining said cache memory and said cache directory; means for requesting a new line of information for a cache line storing an owned line in said cache memory over said packet-switched memory bus; means for copying the owned line of information from the cache line in the cache memory to a pending write-back controller, said pending write-back controller comprising means for buffering said owned line of information from said cache memory; means for storing a write-back address tag and a plurality of status bits for said owned line of information, said write-back address tag being the corresponding main memory address of said owned line of information; means for writing back said owned line of information to said main memory when no read requests for said owned line of information are pending; means for replacing said owned line of information with said requested new line of information in the cache line of the cache memory; and means for writing back said owned line of information in the pending write-back controller to said main memory.
Claim 11
Dependent Claim
294 words
In a computer system including first processor subsystem and a main memory, said first processor subsystem and main memory coupled via a packet-switched memory bus, a write-back cache memory system in said first processor subsystem, said write-back cache memory system comprising: a cache memory, said cache memory comprising more than one cache line, each of said cache lines storing lines of information, each of said lines of information having a corresponding main memory address; a cache directory, said cache directory storing an address tag and a set of status bits for each cache line in said cache memory, said address tag being the corresponding main memory address for said cache line; a write-back cache control system, said write-back cache control system maintaining said cache memory and said cache directory; means for requesting a new line of information for a cache line storing an owned line in said cache memory over said packet-switched memory bus; means for copying the owned line of information from the cache line in the cache memory to a pending write-back controller, said pending write-back controller comprising means for buffering said owned line of information from said cache memory; means for storing a write-back address tag and a plurality of status bits for said owned line of information, said write-back address tag being the corresponding main memory address of said owned line of information; means for writing back said owned line of information to said main memory when no read requests for said owned line of information are pending; means for replacing said owned line of information with said requested new line of information in the cache line of the cache memory; and means for writing back said owned line of information in the pending write-back controller to said main memory.
Claim 12
Dependent Claim
73 words
The write-back cache memory system as claimed in claim 9 wherein said pending write-back controller further comprises: means for receiving and storing at least one read request from a second processor subsystem, said read request requesting the owned line of information; means for replying to said read request from said second processor subsystem with a read request reply to said second processor subsystem, said read request reply containing said owned line of information.
Claim 13
Dependent Claim
29 words
The write-back cache memory system as claimed in claim 10 wherein said plurality of status bits in said pending write-back controller comprise a valid bit and an owned bit.
Claim 14
Dependent Claim
72 words
The write-back cache memory system as claimed in claim 11 wherein said pending write-back controller further comprises: means for receiving a plurality of write requests, said write requests writing to the main memory address of the owned line of information; means for responding to said write requests by resetting the owned bit of the owned line of information such that said owned line of information is not written back to main memory.
Claim 15
Dependent Claim
35 words
The write-back cache memory system as claimed in claim 12 wherein each of said cache lines are further subdivided into M subblocks, each of said subblocks of said cache lines handled as individual memory blocks.
Claim 16
Independent Claim
176 words
A method for a computer system including a first processor subsystem and a main memory coupled via a packet-switched memory bus, said first processor subsystem having a write-back cache memory system comprising a cache memory having more than one cache line, a method of replacing the cache lines in the first processor subsystem cache memory, said method for computer system comprising the steps of: requesting a new line of information for a first cache line in said first processor subsystem cache memory over said packet-switched memory bus; transferring an owned line of information from the first cache line of said processor subsystem cache memory to a pending write-back controller, said pending write-back controller buffering said owned line of information; receiving said requested new line of information into the first cache line of said first processor subsystem cache memory; writing back said owned line of information buffered in the pending write-back controller to the main memory, said step of writing back said owned line of information occurring after said step of requesting said new line of information.
Claim 17
Independent Claim
176 words
A method for a computer system including a first processor subsystem and a main memory coupled via a packet-switched memory bus, said first processor subsystem having a write-back cache memory system comprising a cache memory having more than one cache line, a method of replacing the cache lines in the first processor subsystem cache memory, said method for computer system comprising the steps of: requesting a new line of information for a first cache line in said first processor subsystem cache memory over said packet-switched memory bus; transferring an owned line of information from the first cache line of said processor subsystem cache memory to a pending write-back controller, said pending write-back controller buffering said owned line of information; receiving said requested new line of information into the first cache line of said first processor subsystem cache memory; writing back said owned line of information buffered in the pending write-back controller to the main memory, said step of writing back said owned line of information occurring after said step of requesting said new line of information.
Claim 18
Dependent Claim
100 words
The method for computer system including method of replacing the cache lines in the first processor subsystem cache memory as claimed in claim 14 wherein said step of writing back said owned line of information in the pending write-back controller further comprises: receiving read requests for the owned line of information from a second processor subsystem coupled to said packet-switched memory bus; and responding to said read requests for the owned line of information from said second processor subsystem by sending a read request reply to said second processor subsystem, said read request reply containing the owned line of information.
Claim 19
Dependent Claim
87 words
The method of replacing the cache lines in the first processor subsystem cache memory as claimed in claim 15 wherein said step of writing back said owned line of information in the pending write-back controller further comprises: receiving write requests to the owned line of information from a second processor subsystem coupled to said packet-switched memory bus; and responding to said write requests to the owned line of information from said second processor subsystem by not writing back said owned line of information to the main memory.
Claim 20
Dependent Claim
44 words
The method of replacing the cache lines in the first processor subsystem cache memory as claimed in claim 16 wherein each of said cache lines are further subdivided into M subblocks, each of said subblocks of said cache lines handled as individual memory blocks.
References Cited (Backward Citations)
WO1990005953A1
Cited
US5247648A
Cited
EP0468831A2
Cited
US5263144A
Cited
US5347648A
Cited
US5265235A
Cited
US5303362A
Cited
US5265233A
Cited
US5313609A
Cited
US5325504A
Cited
US5353424A
Cited
US5355471A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |