Throttling circuit for a data transfer system

Claim 1

A data transfer system, comprising: (A) a buffer for storing data to be transferred, wherein the buffer generates a first indication signal when the buffer stores substantially a last data packet and a second indication signal when the buffer is empty; (B) a register circuit coupled to the buffer for receiving the data from the buffer by asserting a request signal; (C) a throttling circuit coupled to the buffer and the register circuit for (1) allowing transfer of the last data packet to the register circuit when the throttling circuit receives the first indication signal and (2) stopping data transmission from the buffer to the register circuit as soon as the last data packet is transferred and before the throttling circuit receives the second indication signal, wherein the throttling circuit asserts an acknowledge signal to deassert the request signal whenever a data packet has been transferred to the register circuit, wherein the throttling circuit further comprises (i) a delay circuit coupled to receive the acknowledge signal of a previously transferred data packet for delaying the acknowledge signal for a predetermined time period during which the last data packet is transferred; (ii) a logic gate coupled to the delay circuit and the register circuit for allowing the first indication signal to pass through only when the delayed acknowledge signal is asserted; (iii) an OR gate coupled to receive the second indication signal and an output of the logic gate; (iv) a logic circuit coupled to receive the request signal and an output of the OR gate for deasserting the acknowledge signal when the output of the OR gate is logically active regardless of the request signal.