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US5434869A
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Test pattern generating apparatus
Assignee: Panasonic Holdings Corp
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Filing: 1992-08-28
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Granted: 1995-07-18
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Expires: 2012-08-28
Abstract
Abstract A test pattern generating apparatus for generating test patterns to test a sequential circuit having at least one memory element. The apparatus calculates, in response to a primary input applied to the sequential circuit, analog logic values for signal lines in the sequential circuit using a nonlinear function, then stores history data for the analog logic values with an inverse covariance matrix of the analog logic values. The apparatus then calculates an evaluation value according to the degree of variance between the analog logic values and the history data. A primary input setting unit is used for producing a next primary input a memory is included for sequentially storing the primary which provides a maximum evaluation value from the evaluation value obtained from the present primary input.a memory is included for sequentially storing the primary inputs produced by the primary input setting unit.
Inventors
- 👤 Hidetsugu Maekawa
- 👤 Yasuharu Shimeki
- 👤 Kazuhiro Kayashima
- 👤 Hisao Niwa
- 👤 Seiichi Shin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:49
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318392
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
209 words
A test pattern generating apparatus for generating test patterns for testing a sequential circuit having at least one memory element, at least one logic element and a plurality of signal lines, said test pattern generating apparatus comprising: an analog logic values calculation means for calculating, in response to a primary input applied to the sequential circuit, an analog logic values of the signal lines in the sequential circuit by a nonlinear function; a data quantity calculation means for storing a history data of the analog logic values of the signal lines with an inverse covariance matrix of the analog logic values; an evaluation value calculation means for receiving said history data from said data quantity calculation means for calculating an evaluation value according to a degree of variance between the analog logic values and the history data; a primary input setting means for receiving said evaluation value from said evaluation value calculation means and for producing a next primary input which provides a maximum evaluation value from the evaluation value obtained from the applied primary input; and a memory means for sequentially storing the next primary input produced by said primary input setting means, whereby the next primary input stored in said memory means serves as a test pattern.
Claim 2
Dependent Claim
209 words
A test pattern generating apparatus for generating test patterns for testing a sequential circuit having at least one memory element, at least one logic element and a plurality of signal lines, said test pattern generating apparatus comprising: an analog logic values calculation means for calculating, in response to a primary input applied to the sequential circuit, an analog logic values of the signal lines in the sequential circuit by a nonlinear function; a data quantity calculation means for storing a history data of the analog logic values of the signal lines with an inverse covariance matrix of the analog logic values; an evaluation value calculation means for receiving said history data from said data quantity calculation means for calculating an evaluation value according to a degree of variance between the analog logic values and the history data; a primary input setting means for receiving said evaluation value from said evaluation value calculation means and for producing a next primary input which provides a maximum evaluation value from the evaluation value obtained from the applied primary input; and a memory means for sequentially storing the next primary input produced by said primary input setting means, whereby the next primary input stored in said memory means serves as a test pattern.
Claim 3
Dependent Claim
133 words
A test pattern generating apparatus as claimed in claim 1, further comprising: a differential calculation means for calculating a differential value of every signal lines in the sequential circuit; and an evaluation value differential coefficient calculation means for receiving said history data from said data quantity calculation means, said differential value from said differential calculation means and said analog logic value from said analog logic value calculation means for calculating a differential coefficient indicative of a search direction of the primary input maximizing the evaluation value in response to each application of primary input; said primary input setting means producing a number of entries of primary inputs each based on a respective differential coefficient and selecting one entry which produces a maximum evaluation value from the evaluation values obtained in a previous cycle.
Claim 4
Dependent Claim
55 words
A test pattern generating apparatus as claimed in claim 1, wherein said primary input setting means produces a number of primary inputs which differ from the previous primary input by a Hamming distance of 1, and selects one primary input which produces a maximum evaluation value from the evaluation value obtained in a previous cycle.
Claim 5
Dependent Claim
31 words
A test pattern generating apparatus as claimed in claim 1, wherein the analog logic value calculation means uses a monotone increasing function as the nonlinear function for obtaining analog logic values.
Claim 6
Dependent Claim
37 words
A test pattern generating apparatus as claimed in claim 1, wherein each of the data quantity calculation means and evaluation value calculation means receives the analog logic values from all the signal lines in the sequential circuit.
Claim 7
Dependent Claim
51 words
A test pattern generating apparatus as claimed in claim 1, wherein each of the data quantity calculation means and evaluation value calculation means receives the analog logic values from input signal lines of the memory element as pseudo-primary outputs and from primary output lines of the sequential circuit as primary outputs.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |