Patent USH1155H successfully refreshed from Google Patents.
EP0342787A2
Expired / Lapsed
EP
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Search method for generating test vectors for sequential logic circuits
Assignee: AT&T Inc
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Filing: 1989-04-06
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Granted: —
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Expires: 2009-04-06
Abstract
Abstract A method for developing a test sequence and for testing manufactured digital circuits. Test vectors are developed based on a simulation-based, directed-search approach. Specifically, from a given test vector, a next test vector is developed by altering the given test vector and determining the utility of the altered trial vector in propagating circuit faults to the primary outputs, based on a simulation of the circuit and a preselected cost function. The vector set is created through an iterative process of altering an accepted test vector to develop a next trial vector. The vector set is efficiently developed by employing one phase that treats the entire set of circuit faults as the target, followed by another phase that targets specific faults that have not been detected in the previous phase.
Inventors
- 👤 Prathima Agrawal
- 👤 Vishwani Deo Agrawal
- 👤 Kwang Ting Cheng
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 16:48
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318307
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
55 words
A method for manufacturing a sequential circuit COMPRISING a step of fabricating said circuit; and a step of testing the operational integrity of said circuit with a test comprising a sequence of input signals created through iterative use of a simulation of said circuit with a cost-directed process of selecting signal members of the sequence.
Claim 2
Independent Claim
55 words
A method for manufacturing a sequential circuit COMPRISING a step of fabricating said circuit; and a step of testing the operational integrity of said circuit with a test comprising a sequence of input signals created through iterative use of a simulation of said circuit with a cost-directed process of selecting signal members of the sequence.
Claim 3
Dependent Claim
171 words
The method of claim 1 wherein said sequence comprises three subsequences, wherein: the first subsequence is developed to preset said circuit to a known state through an iterative process of circuit simulation with a trial vector and selecting the trial vector for the first subsequence when a cost measure that reflects the progress of setting the memory states in the circuit is improved; and the second subsequence is developed through an iterative process of fault simulation of all faults in the circuit with a trial vector and selecting the trial vector for the second subsequence when a cost measure that reflects the progress of circuit faults toward the primary outputs of the circuit is improved; and the third subsequence is developed through an iterative process of selecting a circuit fault to be detected, simulating the circuit's response to a trial vector, and selecting the trial vector for the third subsequence when a cost measure that reflects the progress of the selected fault toward the primary outputs of the circuit is improved.
Claim 4
Dependent Claim
17 words
The method of claim 2 wherein the cost measure is different for each of the three subsequences.
Claim 5
Dependent Claim
18 words
The method of claim 3 wherein a trial vector is deterministically developed from the immediately previous trial vector.
Claim 6
Independent Claim
42 words
A method for developing a test sequence to verify the operational status of a sequential circuit comprising a step of simulating said circuit with trial vectors and selecting trial vectors for said sequence in accordance with said simulation, via a cost-directed process.
Claim 7
Independent Claim
42 words
A method for developing a test sequence to verify the operational status of a sequential circuit comprising a step of simulating said circuit with trial vectors and selecting trial vectors for said sequence in accordance with said simulation, via a cost-directed process.
Claim 8
Dependent Claim
172 words
The method of claim 5 wherein said test sequence comprises three subsequences, wherein: the first subsequence is developed to preset said circuit to a known state through an iterative process of circuit simulation with a trial vector and selecting the trial vector for the first subsequence when a cost measure that reflects the progress of setting the memory states in the circuit is improved; and the second subsequence is developed through an iterative process of fault simulation of all faults in the circuit with a trial vector and selecting the trial vector for the second subsequence when a cost measure that reflects the progress of circuit faults toward the primary outputs of the circuit is improved; and the third subsequence is developed through an iterative process of selecting a circuit fault to be detected, simulating the circuit's response to a trial vector, and selecting the trial vector for the third subsequence when a cost measure that reflects the progress of the selected fault toward the primary outputs of the circuit is improved.
Claim 9
Dependent Claim
17 words
The method of claim 6 wherein the cost measure is different for each of the three subsequences.
Claim 10
Dependent Claim
55 words
A sequential circuit manufactured with a quality assurance step of testing the circuit with a sequence of input signals applied to the circuit's input ports, CHARACTERIZED IN THAT said sequence of input signals is created through iterative use of a simulation of said circuit with a cost-directed process of selecting signal members of the sequence.
Claim 11
Dependent Claim
55 words
A sequential circuit manufactured with a quality assurance step of testing the circuit with a sequence of input signals applied to the circuit's input ports, CHARACTERIZED IN THAT said sequence of input signals is created through iterative use of a simulation of said circuit with a cost-directed process of selecting signal members of the sequence.
Claim 12
Dependent Claim
36 words
A circuit-checking signal set CHARACTERIZED BY signal set members, each of which is derived through iterative use of a simulation of a given sequential circuit with a cost-directed process of selecting signal members of the sequence.
Claim 13
Dependent Claim
36 words
A circuit-checking signal set CHARACTERIZED BY signal set members, each of which is derived through iterative use of a simulation of a given sequential circuit with a cost-directed process of selecting signal members of the sequence.
References Cited (Backward Citations)
No citation records indexed.
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