US5434526A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output circuit and semiconductor integrated circuit device
Assignee: Kyushu Fujitsu Electronics Ltd
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Filing: 1994-08-02
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Granted: 1995-07-18
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Expires: 2014-08-02
Abstract
Abstract The present invention relates to an output circuit and a semiconductor integrated circuit. It is an object of the present invention to cut off a passage of a current through a forward parasitic diode of a transistor connected to a power supply line and a ground line at a time of suspension of output operation of the relevant circuit, and to raise an output high level to the utmost and lower an output low level to the utmost at time of normal output operation. A complementary MOS high impedance output circuit composed of a first field effect transistor and a second field effect transistor is structured so as to include provision of a third field effect transistor for controlling one of a state of a backgate of the first field effect transistor and a state of a backgate of the second field effect transistor and also to include provision of a fourth field effect transistor for controlling one of the state of the backgate of the first and second field effect transistor complementarily to the control of the state of the backgate of the third field effect transistor.
Inventors
- 👤 Syouichi Tanigashira
- 👤 Fumitaka Asami
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:45
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0013; H03K19/003; H03K19/00315; H03K19/00346; H03K19/00361; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
312 words
An output circuit connected between first and second power supply lines of different, respective power source potentials and receiving complementary input signals and having an output terminal, said output circuit comprising: a first field effect transistor of a first conductivity type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of said first conductivity type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the complementary input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, each of said first, second and third field effect transistors is an n-type field effect transistor; the first end of the channel of said third field effect transistor is connected to the first backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate is connected to one of the first power supply line and the first gate; the third backgate is connected to one of the second power supply line and the first backgate; and the second backgate is connected to the second power supply line.
Claim 2
Dependent Claim
312 words
An output circuit connected between first and second power supply lines of different, respective power source potentials and receiving complementary input signals and having an output terminal, said output circuit comprising: a first field effect transistor of a first conductivity type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of said first conductivity type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the complementary input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, each of said first, second and third field effect transistors is an n-type field effect transistor; the first end of the channel of said third field effect transistor is connected to the first backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate is connected to one of the first power supply line and the first gate; the third backgate is connected to one of the second power supply line and the first backgate; and the second backgate is connected to the second power supply line.
Claim 3
Dependent Claim
161 words
The output circuit according to claim 1, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistor is an n-type field effect transistor; the third gate is connected to the first power supply line; the first end of the channel of said fourth field effect transistor is connected to the first backgate and the second end of the channel of said fourth field effect transistor is connected to said second power supply line; the fourth backgate is connected to the second power supply line; and the fourth gate is connected to the second gate.
Claim 4
Dependent Claim
159 words
The output circuit according to claim 1, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistor is an n-type field effect transistor; the third gate is connected to the first gate; the first end of the channel of said fourth field effect transistor is connected to the first backgate and the second end of the channel of said fourth field effect transistor is connected to said second power supply line; the fourth backgate is connected to the second power supply line; and the fourth gate is connected to the second gate.
Claim 5
Dependent Claim
312 words
An output circuit connected between first and second power supply lines of different, respective power source potentials and receiving complementary input signals and having an output terminal, said output circuit comprising: a first field effect transistor of a first conductivity type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of said first conductivity type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the complementary input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, each of said first, second and third field effect transistors is a p-type field effect transistor; the first backgate is connected to the first power supply line; the first end of the channel of said third field effect transistor is connected to the second backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate is connected to one of the second power supply line and the second gate; and the third backgate is connected to one of the first power supply line and the second backgate.
Claim 6
Dependent Claim
312 words
An output circuit connected between first and second power supply lines of different, respective power source potentials and receiving complementary input signals and having an output terminal, said output circuit comprising: a first field effect transistor of a first conductivity type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of said first conductivity type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the complementary input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, each of said first, second and third field effect transistors is a p-type field effect transistor; the first backgate is connected to the first power supply line; the first end of the channel of said third field effect transistor is connected to the second backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate is connected to one of the second power supply line and the second gate; and the third backgate is connected to one of the first power supply line and the second backgate.
Claim 7
Dependent Claim
161 words
The output circuit according to claim 4, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistor is a p-type field effect transistor; the third gate is connected to the second power supply line; the first end of the channel of said fourth field effect transistor is connected to the second backgate and the second end of the channel of said fourth field effect transistor is connected to said first power supply line; the fourth backgate is connected to the first power supply line; and the fourth gate is connected to the first gate.
Claim 8
Dependent Claim
159 words
The output circuit according to claim 4, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistor is a p-type field effect transistor; the third gate is connected to the second gate; the first end of the channel of said fourth field effect transistor is connected to the second backgate and the second end of the channel of said fourth field effect transistor is connected to said first power supply line; the fourth backgate is connected to the first power supply line; and the fourth gate is connected to the first gate.
Claim 9
Dependent Claim
321 words
An output circuit connected between first and second power supply lines respectively of relatively high and low potentials and receiving identical input signals and having an output terminal, said output circuit comprising: a first field effect transistor of n-type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of p-type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the identical input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, each of said first and third field effect transistors is an n-type field effect transistor; said second field effect transistor is a p-type field effect transistor; the first end of the channel of said third field effect transistor is connected to the first backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate of said third field effect transistor is connected to one of the first power supply line and the first gate; the third backgate is connected to one of the second power supply line and the first backgate; and the second backgate is connected to said output terminal.
Claim 10
Dependent Claim
321 words
An output circuit connected between first and second power supply lines respectively of relatively high and low potentials and receiving identical input signals and having an output terminal, said output circuit comprising: a first field effect transistor of n-type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of p-type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the identical input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, each of said first and third field effect transistors is an n-type field effect transistor; said second field effect transistor is a p-type field effect transistor; the first end of the channel of said third field effect transistor is connected to the first backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate of said third field effect transistor is connected to one of the first power supply line and the first gate; the third backgate is connected to one of the second power supply line and the first backgate; and the second backgate is connected to said output terminal.
Claim 11
Dependent Claim
170 words
The output circuit according to claim 7, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistor is an n-type field effect transistor; the third gate is connected to the first power supply line; the first end of the channel of said fourth field effect transistor is connected to the first backgate and the second end of the channel of said fourth field effect transistor is connected to said second power supply line; the fourth backgate is connected to the second power supply line; and the fourth gate receives a corresponding input signal that is inverted with respect to the identical input signals.
Claim 12
Dependent Claim
168 words
The output circuit according to claim 7, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistors is an n-type field effect transistor; the third gate is connected to the first gate; the first end of the channel of said fourth field effect transistor is connected to the first backgate and the second end of the channel of said fourth field effect transistor is connected to said second power supply line; the fourth backgate is connected to the second power supply line; and the fourth gate receives a corresponding input signal that is inverted with respect to the identical input signals.
Claim 13
Dependent Claim
315 words
An output circuit connected between first and second power supply lines respectively of relatively high and low potentials and receiving identical input signals and having an output terminal, said output circuit comprising: a first field effect transistor of n-type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of p-type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the identical input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, said first field effect transistor is an n-type field effect transistor; each of said second and third field effect transistors is a p-type field effect transistor; said first backgate is connected to said output terminal; the first end of the channel of said third field effect transistor is connected to the second backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate is connected to one of the second power supply line and the second gate; and the third backgate is connected to one of the first power supply line and the second backgate.
Claim 14
Dependent Claim
315 words
An output circuit connected between first and second power supply lines respectively of relatively high and low potentials and receiving identical input signals and having an output terminal, said output circuit comprising: a first field effect transistor of n-type having a first gate, a first backgate and a channel, the channel having a first end connected to the first power supply line and a second end, comprising a drain junction, connected to the output terminal; a second field effect transistor of p-type having a second gate, a second backgate and a channel, the channel having a first end connected to said drain junction of said first field effect transistor and a second end connected to the second power supply line and thereby being connected in series with the channel of said first field effect transistor between the first and second power supply lines; said first and second gates respectively receiving the identical input signals; a third field effect transistor having a third gate, a third backgate and a channel, the channel having a first end connected to one of said first and second backgates and a second end connected to said output terminal, said third field effect transistor controlling said one of said first and second backgates; wherein, said first field effect transistor is an n-type field effect transistor; each of said second and third field effect transistors is a p-type field effect transistor; said first backgate is connected to said output terminal; the first end of the channel of said third field effect transistor is connected to the second backgate and the second end of the channel of said third field effect transistor is connected to said output terminal; the third gate is connected to one of the second power supply line and the second gate; and the third backgate is connected to one of the first power supply line and the second backgate.
Claim 15
Dependent Claim
170 words
The output circuit according to claim 10, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistor is a p-type field effect transistor; the third gate is connected to the second power supply line; the first end of the channel of said fourth field effect transistor is connected to the second backgate and the second end of the channel of said fourth field effect transistor is connected to said first power supply line; the fourth backgate is connected to the first power supply line; and the fourth gate receives a corresponding input signal that is inverted with respect to the identical input signals.
Claim 16
Dependent Claim
168 words
An output circuit according to claim 10, further comprising: a fourth field effect transistor having a fourth gate, a fourth backgate and a channel, the channel having a first end connected to said one of said first and second backgates and a second end connected to one of the first and second power supply lines, said fourth field effect transistor operating complementarily with said third field effect transistor and controlling said one of said first and second backgates; wherein, said fourth field effect transistor is a p-type field effect transistor; the third gate is connected to the second gate; the first end of the channel of said fourth field effect transistor is connected to the second backgate and the second end of the channel of said fourth field effect transistor is connected to said first power supply line; the fourth backgate is connected to the first power supply line; and the fourth gate receives a corresponding input signal that is inverted with respect to the identical input signals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-17 | 1999-01-16 | 1999-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-17 | 2003-01-16 | 2003-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-17 | 2007-01-16 | 2007-07-18 | $7700.00 | Window Closed / Lapsed |