Method for fabricating self-aligned polysilicon contacts on FET source/drain areas

Claim 1

A method for fabricating N-channel and P-channel field effect transistors having self-aligned polysilicon pad source and drain contacts, comprising the steps of: providing a semiconductor substrate with doped P-well and N-well device areas formed therein and a gate oxide formed thereon with isolation field oxide areas formed elsewhere on said substrate; depositing a first polysilicon layer on said substrate; and doping by implantation said first polysilicon layer; depositing a first insulating layer on said first polysilicon layer; and patterning said first polysilicon layer and first insulating layer, thereby forming gate electrodes on said P-well and N-well device areas; doping by implantation with N-type dopant ions portions of said P-well device areas and forming N-type source and drain diffused areas and thereby forming the lightly doped drain (LDD) for the N-channel FET; doping by implantation with P-type dopant ions portions of said N-well device areas and forming P-type source and drain diffused areas and thereby forming the lightly doped drain (LDD) for the P-channel FET; depositing a conformal sidewall insulating layer on said substrate and anisotropically etching back to the surface of said first insulating layer and thereby forming sidewall spacers on said gate electrodes; depositing a second polysilicon layer over said substrate and thereby coating said gate electrodes and said P-well and N-well devices area; patterning said second polysilicon layer leaving portions over said N-type and P-type source and drain areas and removing said layer elsewhere on said substrate, thereby forming polysilicon pads over said source and drain areas; doping by implanting with N-type dopant ions said polysilicon pads selectively over said N-type source and drain areas and doping said polysilicon pads with P-type dopant ions over said P-type source and drain areas; annealing by heating said substrate and thereby diffusing in said dopant ions from said polysilicon pad into said source and drain areas and forming contacts; depositing a second insulating layer over said polysilicon pads and elsewhere on said substrate; forming openings in said second insulating layer over said polysilicon pads and completing said N-channel and P-channel field effect transistors having contact openings.

Claim 2

A method for fabricating N-channel and P-channel field effect transistors having self-aligned polysilicon pad source and drain contacts, comprising the steps of: providing a semiconductor substrate with doped P-well and N-well device areas formed therein and a gate oxide formed thereon with isolation field oxide areas formed elsewhere on said substrate; depositing a first polysilicon layer on said substrate; and doping by implantation said first polysilicon layer; depositing a first insulating layer on said first polysilicon layer; and patterning said first polysilicon layer and first insulating layer, thereby forming gate electrodes on said P-well and N-well device areas; doping by implantation with N-type dopant ions portions of said P-well device areas and forming N-type source and drain diffused areas and thereby forming the lightly doped drain (LDD) for the N-channel FET; doping by implantation with P-type dopant ions portions of said N-well device areas and forming P-type source and drain diffused areas and thereby forming the lightly doped drain (LDD) for the P-channel FET; depositing a conformal sidewall insulating layer on said substrate and anisotropically etching back to the surface of said first insulating layer and thereby forming sidewall spacers on said gate electrodes; depositing a second polysilicon layer over said substrate and thereby coating said gate electrodes and said P-well and N-well devices area; patterning said second polysilicon layer leaving portions over said N-type and P-type source and drain areas and removing said layer elsewhere on said substrate, thereby forming polysilicon pads over said source and drain areas; doping by implanting with N-type dopant ions said polysilicon pads selectively over said N-type source and drain areas and doping said polysilicon pads with P-type dopant ions over said P-type source and drain areas; annealing by heating said substrate and thereby diffusing in said dopant ions from said polysilicon pad into said source and drain areas and forming contacts; depositing a second insulating layer over said polysilicon pads and elsewhere on said substrate; forming openings in said second insulating layer over said polysilicon pads and completing said N-channel and P-channel field effect transistors having contact openings.