Patent US5430686A successfully refreshed from Google Patents.
US5430686A
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Semiconductor memory device and operating method thereof
Assignee: Mitsubishi Electric Corp
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Filing: 1992-10-15
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Granted: 1995-07-04
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Expires: 2012-10-15
Abstract
Abstract In a DRAM, buffer circuits constituting a column address buffer are provided near address input pads receiving external address signals to be input thereto, and switch circuits arranged near the address input pads are connected between the address input pads and a row address buffer. Driving capability of each buffer circuits is set larger than in the prior art. Each switch circuit is controlled to be OFF while a column address signal is being supplied to a corresponding one of the address input pads. While the column address signal is externally applied to the address input pads, the capacitance and resistance of the interconnection layer which affects the waveform of the internal column address signal can be reduced, and hence time required for selecting one column of memory cells in each of memory cell array blocks in response to the external column address signal can be reduced, thus reducing the access time in the DRAM.
Inventors
- 👤 Kenji Tokami
- 👤 Yoshinori Inoue
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/408; G11C11/4082; G11C11/4087
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
173 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns; an address input pad for time divisionally receiving a row address signal designating any of said plurality of rows and a column address signal designating any of said plurality of columns; column address buffer means provided proximate said address input pad for buffering said column address signal applied to said address input pad; row address buffer means for buffering said row address signal applied to said address input pad; row selecting means responsive to an output signal from said row address buffer means for selecting said any row; column selecting means responsive to an output signal from said column address buffer means for selecting said any column; and switching means connected between said row address buffer means and said address input pad, said switching means electrically disconnecting said address input pad from said row address buffer means while said address input pad is receiving said external column address signal.
Claim 2
Dependent Claim
173 words
A semiconductor memory device comprising: a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns; an address input pad for time divisionally receiving a row address signal designating any of said plurality of rows and a column address signal designating any of said plurality of columns; column address buffer means provided proximate said address input pad for buffering said column address signal applied to said address input pad; row address buffer means for buffering said row address signal applied to said address input pad; row selecting means responsive to an output signal from said row address buffer means for selecting said any row; column selecting means responsive to an output signal from said column address buffer means for selecting said any column; and switching means connected between said row address buffer means and said address input pad, said switching means electrically disconnecting said address input pad from said row address buffer means while said address input pad is receiving said external column address signal.
Claim 3
Dependent Claim
72 words
The semiconductor memory device according to claim 1, wherein each of said plurality of memory cells is a dynamic type memory cell; said semiconductor memory device further comprising means for activating said switching means in a mode in which column address signals are successively supplied to said column selecting means through said column address buffer means while any one of said plurality of rows is kept selected by said row selecting means.
Claim 4
Dependent Claim
37 words
The semiconductor memory device according to claim 2, wherein said row address buffer means further has a function of storing said row address signal applied from said address input pad through said switching means in said mode.
Claim 5
Dependent Claim
93 words
The semiconductor memory device according to claim 3, wherein each of said column address signal and said row address signal has a plural bit length; said address input pad includes a plurality of pads provided corresponding to said plural bits; said column address buffer means includes a plurality of first buffer circuits provided corresponding to said plurality of pads; said row address buffer means includes a plurality of second buffer circuits provided corresponding to said plurality of pads; and each of said plurality of first buffer circuits is arranged near the corresponding pad.
Claim 6
Dependent Claim
75 words
The semiconductor memory device according to claim 4, wherein said switching means includes a plurality of switch circuits provided corresponding to said plurality of second buffer circuits, and switch control means for collectively controlling said plurality of switch circuits, each of said plurality of switch circuits being connected between the corresponding one of the second buffer circuits and the pad provided corresponding to said corresponding second buffer circuit and being arranged near said corresponding pad.
Claim 7
Dependent Claim
50 words
The semiconductor memory device according to claim 5, receiving an external control signal for instructing said row address buffer means to take the row address signal, wherein said switch control means turns off said plurality of switch circuits after a prescribed time period, in response to said external control signal.
Claim 8
Dependent Claim
22 words
The semiconductor memory device according to claim 6, wherein said switch control means includes delay means for delaying said external control signal.
Claim 9
Dependent Claim
59 words
The semiconductor memory device according to claim 7, wherein each of said plurality of switch circuits includes a field effect semiconductor element having a first conduction terminal connected to an input end of the corresponding second buffer circuit, a second conduction terminal connected to the corresponding pad and a control terminal receiving an output signal from said delay means.
Claim 10
Dependent Claim
46 words
The semiconductor memory device according to claim 2, further comprising address counter means for generating internal address signals successively designating said plurality of rows for refreshing data in said plurality of memory cells, wherein said row address buffer means is arranged near said address counter means.
Claim 11
Dependent Claim
42 words
The semiconductor memory device according to claim 6, wherein the length of said prescribed time period is set such that said plurality of switch circuits are turned off after said external row address signal is stored by said row address buffer means.
Claim 12
Dependent Claim
81 words
The semiconductor memory device according to claim 6, wherein each of said first buffer circuits includes first inverting means for inverting a signal from the corresponding pad, second inverting means for inverting the potential at an output end of said first inverting means, holding means for holding constant the potential at said output end regardless of change in the level of the signal from said corresponding pad, and means for disabling said holding means in response to said external control signal.
Claim 13
Dependent Claim
64 words
The semiconductor memory device according to claim 7, wherein said plurality of first buffer means are connected to said column selecting means by a plurality of interconnection layers each having capacitance and resistance, respectively, and each of said plurality of first buffer means has driving capability corresponding to the value of the capacitance and the value of the resistance of the corresponding interconnection layer.
Claim 14
Independent Claim
170 words
A method of operating a semiconductor memory device including a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns and a pad for receiving external signals, comprising the steps of: receiving a row address signal designating any of said plurality of rows by said pad; buffering said received row address signal by using a row address buffer provided apart from said pad; selecting one of said plurality of rows in response to said buffered row address signal; after receiving said row address signal by said pad, receiving a column address signal designating any of said plurality of columns by said pad; buffering said received column address signal by using a column address buffer provided near said pad; successively selecting some of said plurality of columns in response to said buffered column address signal while said one row is being selected; and electrically disconnecting said pad from said row address buffer while said column address signal is being received by said pad.
Claim 15
Independent Claim
170 words
A method of operating a semiconductor memory device including a plurality of memory cells arranged in a matrix of a plurality of rows and a plurality of columns and a pad for receiving external signals, comprising the steps of: receiving a row address signal designating any of said plurality of rows by said pad; buffering said received row address signal by using a row address buffer provided apart from said pad; selecting one of said plurality of rows in response to said buffered row address signal; after receiving said row address signal by said pad, receiving a column address signal designating any of said plurality of columns by said pad; buffering said received column address signal by using a column address buffer provided near said pad; successively selecting some of said plurality of columns in response to said buffered column address signal while said one row is being selected; and electrically disconnecting said pad from said row address buffer while said column address signal is being received by said pad.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |