US5274594A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static RAM
Assignee: Micron Memory Japan Ltd
•
Filing: 1992-02-25
•
Granted: 1993-12-28
•
Expires: 2012-02-25
Abstract
Abstract A static RAM comprises: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; and redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit. Load MOSFETs of the complementary data lines are arranged close to the column select circuits to inhibit the column selecting operations by a decoder circuit and turn off the load MOSFETs when fuse means is cut. An access to a defective address is detected by a redundant decoder stored with the defective address, when the fuse means is selectively cut, to select the column select circuits of the redundant circuit.
Inventors
- 👤 Kazumasa Yanagisawa
- 👤 Atsushi Hiraishi
- 👤 Hideyuki Aoki
- 👤 Satoshi Oguchi
- 👤 Sadayuki Ohkuma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:10
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/80; G11C29/83; G11C29/832; G11C29/84
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
135 words
A static RAM comprising: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit; MOSFETs arranged close to said column select circuits and constituting loads of said complementary data lines; a decoder circuit equipped with fuse means for inhibiting the column selecting operations when said fuse means is cut; a load control circuit for turning off said MOSFETs constituting the loads when said fuse means is cut; and a redundant decoder circuit for storing a defective address, when said fuse means is selectively cut, and for selecting said column select circuits in response to an access to the stored defective address.
Claim 2
Dependent Claim
135 words
A static RAM comprising: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit; MOSFETs arranged close to said column select circuits and constituting loads of said complementary data lines; a decoder circuit equipped with fuse means for inhibiting the column selecting operations when said fuse means is cut; a load control circuit for turning off said MOSFETs constituting the loads when said fuse means is cut; and a redundant decoder circuit for storing a defective address, when said fuse means is selectively cut, and for selecting said column select circuits in response to an access to the stored defective address.
Claim 3
Dependent Claim
37 words
A static RAM according to claim 1, wherein the storage of said defective address constitutes a signal path for transmitting an internal address signal or predecode signal equivalently corresponding to said defective address by said fuse means.
Claim 4
Dependent Claim
45 words
A static RAM according to claim 2, wherein said decoder circuit is additionally given a function to turning off the MOSFETs constituting the loads corresponding to the unit which is instructed to select when in a writing operation in response to a write control signal.
Claim 5
Dependent Claim
80 words
A static RAM according to claim 3, wherein one memory mat is formed of the plurality of units and has its word lines selected by a sub-word driver made receptive of a select signal corresponding to a main word line and the memory mat, wherein said main word line is shared among a plurality of memory mats by a main word driver, and wherein the redundant circuit corresponding to the plurality of units is provided around said main word driver.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-12-27 | 1997-06-28 | 1997-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-12-27 | 2001-06-28 | 2001-12-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-12-27 | 2005-06-28 | 2005-12-28 | $7700.00 | Window Closed / Lapsed |