US4587639A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static semiconductor memory device incorporating redundancy memory cells
Assignee: Fujitsu Ltd
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Filing: 1984-03-27
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Granted: 1986-05-06
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Expires: 2004-03-27
Abstract
Abstract In a static semiconductor memory device incorporating redundancy memory cells (C R0 , C R1 , . . . ), a connecting/disconnecting circuit is linked between a power supply terminal (V CC ) and one of bit lines (B 0 , B 0 , . . . ), thereby reducing or cutting off a current flowing through a defective memory cell.
Inventors
- 👤 Keizo Aoyama
- 👤 Teruo Seki
- 👤 Takahiko Yamauchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:23
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/83; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C29/832; G11C7/00; G11C7/12; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
155 words
A static semiconductor memory device comprising: a power supply means; a memory cell array having a plurality of normal memory cell rows or columns each comprising a plurality of memory cells; at least one redundancy memory cell row or column comprising a plurality of redundancy memory cells, said redundancy memory cell row or column being able to replace one of said normal cell rows or columns including a defective cell; a plurality of selecting line means, each connected to either one of said normal memory cell rows or columns, or said redundancy memory cell row or column; and a plurality of connecting/disconnecting means, each linked between one of said selecting line means and said power supply means, said connecting/disconnecting means electrically disconnecting said selecting line means from said power supply means for at least a non-selected mode of said device whereby current is prevented from flowing between said power supply means and said memory cells.
Claim 2
Dependent Claim
155 words
A static semiconductor memory device comprising: a power supply means; a memory cell array having a plurality of normal memory cell rows or columns each comprising a plurality of memory cells; at least one redundancy memory cell row or column comprising a plurality of redundancy memory cells, said redundancy memory cell row or column being able to replace one of said normal cell rows or columns including a defective cell; a plurality of selecting line means, each connected to either one of said normal memory cell rows or columns, or said redundancy memory cell row or column; and a plurality of connecting/disconnecting means, each linked between one of said selecting line means and said power supply means, said connecting/disconnecting means electrically disconnecting said selecting line means from said power supply means for at least a non-selected mode of said device whereby current is prevented from flowing between said power supply means and said memory cells.
Claim 3
Dependent Claim
39 words
A device as set forth in claim 1, further comprising a plurality of additional selecting line means, connected to said memory cells and said redundancy memory cells, said additional selecting line means being perpendicular to said selecting line means.
Claim 4
Dependent Claim
55 words
A device as set forth in claim 2, wherein said connecting/disconnecting means electrically connects said selecting line means to said power supply means for a definite time period after said device is changed from a non-selected mode to a selected mode or after the potential of one of said additional selecting line means is changed.
Claim 5
Dependent Claim
25 words
A device as set forth in claim 1, wherein said connecting/disconnecting means comprises transistors linked between said selecting line means and said power supply means.
Claim 6
Dependent Claim
57 words
A device as set forth in claim 4, wherein each of said transistors comprises an enhancement MIS transistor having a drain connected to said power supply means, a source connected to one of said selecting line means, and a gate, the potential of said gate being controlled so as to turn on and off said MIS transistor.
Claim 7
Dependent Claim
50 words
A device as set forth in claim 4, wherein said connecting/disconnecting means further comprises: fuse means linked between said selecting line means and said transistors; and a melting means for melting said fuse means connectable to one of said selecting line means connected to one or more defective memory cells.
Claim 8
Dependent Claim
50 words
A device as set forth in claim 4, wherein said connecting/disconnecting means further comprises: fuse means linked between said power supply means and said transistors; and a melting means for melting said fuse means connectable to one of said selecting line means connected to one or more defective memory cells.
Claim 9
Dependent Claim
155 words
A static semiconductor memory device comprising: a power supply means; a memory cell array having a plurality of normal memory cell rows or columns each comprising a plurality of memory cells; at least one redundancy memory cell row or column comprising a plurality of redundancy memory cells, said redundancy memory cell row or column being able to replace one of said normal cell rows or columns including a defective cell; a plurality of selecting line means, each connected to either one of said normal memory cell rows or columns, or said redundancy memory cell row or column; a plurality of fuse means, each liked between one of said selecting line means and said power supply means; and a melting means for melting said fuse means connectable to one of said selecting line means connected to one or more defective memory cells to prevent flow of current between said power supply means and said memory cells.
Claim 10
Dependent Claim
155 words
A static semiconductor memory device comprising: a power supply means; a memory cell array having a plurality of normal memory cell rows or columns each comprising a plurality of memory cells; at least one redundancy memory cell row or column comprising a plurality of redundancy memory cells, said redundancy memory cell row or column being able to replace one of said normal cell rows or columns including a defective cell; a plurality of selecting line means, each connected to either one of said normal memory cell rows or columns, or said redundancy memory cell row or column; a plurality of fuse means, each liked between one of said selecting line means and said power supply means; and a melting means for melting said fuse means connectable to one of said selecting line means connected to one or more defective memory cells to prevent flow of current between said power supply means and said memory cells.
Claim 11
Dependent Claim
40 words
A device as set forth in claim 8, further comprising: load transistors each having a drain connected to said power supply means, a source connected to one of said fuse means, and a gate connected to said power supply means.
Claim 12
Dependent Claim
42 words
A device as set forth in claim 8, further comprising: load transistors each having a drain connected to one of said fuse means, a source connected to one of said selecting line means, and a gate connected to said power supply means.
Claim 13
Dependent Claim
42 words
A device as set forth in claim 8, further comprising load transistors each having a drain connected to said power supply means, a source connected to one of said selecting line means, and a gate connected to one of said fuse means.
Claim 14
Dependent Claim
21 words
A device as set forth in claim 1, wherein each of said selecting line means comprises a pair of bit lines.
Claim 15
Dependent Claim
21 words
A device as set forth in claim 8, wherein each of said selecting line means comprises a pair of bit lines.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |