Semiconductor memory having redundant cells

Claim 2

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting said second lines; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; address storage means for storing an address of said defective line to be replaced with said redundancy line when said redundancy line is used; and control means for controlling said selecting means by generating a selecting signal in accordance with said address stored in said address storage means to concurrently select all of said second lines excluding said defective line based on the selecting signal, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 3

A semiconductor memory comprising: first lines; memory cells driven with signals on said first lines; second lines connected with corresponding ones of said memory cells; selecting means coupled with said second lines for selecting said second lines; potential supply means connected with said second lines in common for applying a predetermined potential to all of said second lines; and control means for controlling said selecting means, when a defective line is among said second lines, by generating a selecting signal so as not to apply said potential from said potential supply means to said defective line of said second lines based on the selecting signal, said controlling means also controlling a redundancy line selecting means when a second line is defective.

Claim 4

A semiconductor memory comprising: first lines; memory cells driven with signals on said first lines; second lines connected with corresponding ones of said memory cells; selecting means coupled with said second lines for selecting said second lines; potential supply means connected with said second lines in common for applying a predetermined potential to all of said second lines; and control means for controlling said selecting means, when a defective line is among said second lines, by generating a selecting signal so as not to apply said potential from said potential supply means to said defective line of said second lines based on the selecting signal, said controlling means also controlling a redundancy line selecting means when a second line is defective.

Claim 5

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting a plurality of said second lines in parallel; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; address storage means for storing an address of said defective line to be replaced with said redundancy line when said redundancy line is used for said defective line; and control means for controlling said selecting means, when said plurality of second lines are selected in parallel by said selecting means, by generating a selecting signal in accordance with said address stored in said address storage means to concurrently select all of said plurality of second lines excluding said defective line based on the selecting signal, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 6

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting a plurality of said second lines in parallel; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; address storage means for storing an address of said defective line to be replaced with said redundancy line when said redundancy line is used for said defective line; and control means for controlling said selecting means, when said plurality of second lines are selected in parallel by said selecting means, by generating a selecting signal in accordance with said address stored in said address storage means to concurrently select all of said plurality of second lines excluding said defective line based on the selecting signal, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 7

A semiconductor memory according to claim 1, in which said control means has an operation mode that controls said selecting means to select said second lines excluding said defective line whose address has been stored in said address storage means.

Claim 8

A semiconductor memory according to claim 4, in which said operation mode is a test mode other than a normal data readout mode.

Claim 9

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting said second lines; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; address storage means for storing an address of said defective line to be replaced with said redundancy line when said redundancy line is used; and control means for controlling said selecting means, when said second lines are selected by said selecting means during one of a plurality of operating modes including a test mode other than a normal readout mode, by generating a selecting signal in accordance with said address stored in said address storage means to concurrently select all of said second lines excluding said defective line based on the selecting signal, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 10

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting said second lines; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; address storage means for storing an address of said defective line to be replaced with said redundancy line when said redundancy line is used; and control means for controlling said selecting means, when said second lines are selected by said selecting means during one of a plurality of operating modes including a test mode other than a normal readout mode, by generating a selecting signal in accordance with said address stored in said address storage means to concurrently select all of said second lines excluding said defective line based on the selecting signal, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 11

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting said second lines; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; and control means for controlling said selecting means, when said redundancy line is used and said defective line is selected by said selecting means on the basis of an address signal used for replacing said defective line with said redundancy line, by generating a selecting signal to select all of said second lines excluding said defective line based on the selecting signal during one of a plurality of operating modes including a test mode other than a normal readout mode, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 12

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting said second lines; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; and control means for controlling said selecting means, when said redundancy line is used and said defective line is selected by said selecting means on the basis of an address signal used for replacing said defective line with said redundancy line, by generating a selecting signal to select all of said second lines excluding said defective line based on the selecting signal during one of a plurality of operating modes including a test mode other than a normal readout mode, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 13

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting said second lines; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; and control means for controlling said selecting means, when said redundancy line is used and said defective line is selected by said selecting means on the basis of an address signal used for replacing said defective line with said redundancy line, by generating a selecting signal to concurrently select all of said second lines excluding said defective line based on the selecting signal, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 14

A semiconductor memory comprising: a memory cell array including memory cells at intersections of first lines and second lines; selecting means coupled with said second lines for selecting said second lines; potential supply means coupled with said second lines through said selecting means for applying a predetermined potential to said second lines; at least one redundancy line for use when a defective line is among said second lines, to replace said defective line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; and control means for controlling said selecting means, when said redundancy line is used and said defective line is selected by said selecting means on the basis of an address signal used for replacing said defective line with said redundancy line, by generating a selecting signal to concurrently select all of said second lines excluding said defective line based on the selecting signal, said controlling means also controlling said redundancy line selecting means when said redundancy line is used.

Claim 15

A semiconductor memory according to claim 8, in which said control means has an operation mode that controls said selecting means to select said second lines excluding said defective line which is designated by said address signal.

Claim 16

A semiconductor memory according to claim 9, in which said operation mode is a test mode other than a normal data readout mode.

Claim 17

A semiconductor memory according to any one of claims 8 to 10, in which said second lines are bit lines.

Claim 18

A semiconductor memory according to any one of claims 8 to 10, in which each of said memory cells comprises a source region, a drain region, a floating gate formed over a channel region between said source region and said drain region, and a control gate formed over said floating gate, said memory cells storing data in accordance with a quantity of charges stored on said floating gate.

Claim 19

A semiconductor memory comprising: a memory cell array including memory cells at intersections of word lines and bit lines, each of said memory cells comprising a source region, a drain region, a floating gate formed over a channel region between said source region and said drain region, and a control gate formed over said floating gate, and storing data in accordance with a quantity of charges stored on said floating gate; bit-line selecting means coupled with said bit lines for selecting said bit lines; potential supply means coupled with said bit lines through said bit-line selecting means for applying a predetermined potential to said bit lines; at least one redundancy line for use when a defective line is among said bit lines, to replace said defective bit line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; address storage means for storing an address used for replacing said defective bit line with said redundancy line when said redundancy line is used; and control means for controlling said bit-line selecting means, when said bit lines are selected in parallel by said bit-line selecting means in a test mode other than a normal data readout mode, by generating a selecting signal in accordance with said address stored in said address storage means to concurrently select all of said bit lines excluding said defective bit line based on the selecting signal.

Claim 20

A semiconductor memory comprising: a memory cell array including memory cells at intersections of word lines and bit lines, each of said memory cells comprising a source region, a drain region, a floating gate formed over a channel region between said source region and said drain region, and a control gate formed over said floating gate, and storing data in accordance with a quantity of charges stored on said floating gate; bit-line selecting means coupled with said bit lines for selecting said bit lines; potential supply means coupled with said bit lines through said bit-line selecting means for applying a predetermined potential to said bit lines; at least one redundancy line for use when a defective line is among said bit lines, to replace said defective bit line; redundancy line selecting means for selecting said redundancy line when said redundancy line is to be used; address storage means for storing an address used for replacing said defective bit line with said redundancy line when said redundancy line is used; and control means for controlling said bit-line selecting means, when said bit lines are selected in parallel by said bit-line selecting means in a test mode other than a normal data readout mode, by generating a selecting signal in accordance with said address stored in said address storage means to concurrently select all of said bit lines excluding said defective bit line based on the selecting signal.

Claim 21

A semiconductor memory comprising: word lines; memory cells driven with signals on said word lines, each of said memory cells comprising a source region, a drain region, a floating gate formed over a channel region between said source region and said drain region, and a control gate formed over said floating gate, and storing data in accordance with a quantity of charges stored on said floating gate; bit lines each connected with corresponding ones of said memory cells; selecting means coupled with said bit lines for selecting said bit lines; potential supply means connected with said bit lines in common for applying a predetermined potential to all of said bit lines; and control means for controlling said selecting means, when a defective bit line among said bit lines in a test mode other than a normal data readout mode, by generating a selecting signal so as not to apply said potential from said potential supply means to said defective bit line based on the selecting signal.

Claim 22

A semiconductor memory comprising: word lines; memory cells driven with signals on said word lines, each of said memory cells comprising a source region, a drain region, a floating gate formed over a channel region between said source region and said drain region, and a control gate formed over said floating gate, and storing data in accordance with a quantity of charges stored on said floating gate; bit lines each connected with corresponding ones of said memory cells; selecting means coupled with said bit lines for selecting said bit lines; potential supply means connected with said bit lines in common for applying a predetermined potential to all of said bit lines; and control means for controlling said selecting means, when a defective bit line among said bit lines in a test mode other than a normal data readout mode, by generating a selecting signal so as not to apply said potential from said potential supply means to said defective bit line based on the selecting signal.

Claim 23

A semiconductor memory according to claim 2, in which said control means has an operation mode that controls said selecting means to select said second lines excluding said defective line whose address has been stored in said address storage means.

Claim 24

A semiconductor memory according to claim 3, in which said control means has an operation mode that controls said selecting means to select said second lines excluding said defective line whose address has been stored in said address storage means.

Claim 25

A semiconductor memory according to claim 15, in which said operation mode is a test mode other than a normal data readout mode.

Claim 26

A semiconductor memory according to claim 16 in which said operation mode is a test mode other than a normal data readout mode.

Claim 27

A semiconductor memory according to any one of claims 1 to 5, or 15 to 18 in which said second lines are bit lines.

Claim 28

A semiconductor memory according to any one of claims 1 to 5, or 15 or 18 in which each of said memory cells comprises a source region, a drain region, a floating gate formed over a channel region between said source region and said drain region, and a control gate formed over said floating gate, said memory cells storing data in accordance with a quantity of charges stored on said floating gate.