Architecture for a flash erase EEPROM memory

Claim 2

A memory device comprising: a memory cell comprising: a source region; a drain region located apart from said source region; a channel region located between said source and said drain regions; a floating gate electrode above and insulated from said channel region sufficiently close to said source region to allow charge transfer between said floating gate electrode and that portion of said channel region adjacent said source region, and sufficiently distant from said drain region to prevent charge transfer between said floating gate electrode and that portion of said channel region adjacent said drain region; and a control gate electrode located above said channel region and said floating gate electrode and insulated from said channel region and said floating gate electrode; programming means connected to said source region for selectively causing a change in the charge stored on said floating gate electrode, thereby altering the control gate threshold voltage of said memory cell; and reading means connected to said drain region for determining the amount of current flow through said channel region in response to the application of a set of read voltages to said control gate electrode, source region, and drain region.

Claim 3

A structure as in claim 1 wherein said source region is doped to a sufficient high doping level to increase hot electron injection from that portion of said channel region near said source region to said floating gate during programming.

Claim 4

A structure as in claims 1 or 2 wherein said drain region is doped to a sufficiently low doping level to reduce parasitic drain capacitance.

Claim 5

A structure as in claim 1 wherein said reading means comprises transistors having breakdown voltages less than the programming voltage applied by said programming means to said source region during programming.

Claim 6

A structure as in claim 1 which further comprises a source field region adjacent at least a portion of said source region not adjacent said channel region, said source field region being not heavily doped, thereby increasing the gated diode breakdown voltage of said region.

Claim 7

A structure as in claims 1 or 5 which further comprises a drain field region adjacent at least a portion of said drain region not adjacent said channel region, said drain field region being relatively highly doped, thereby increasing the isolation of said drain region.

Claim 8

A structure as in claim 1 wherein said programming means serves to add electrons to said floating gate electrode, thereby altering the control gate threshold voltage of said memory transistor in a first direction, and also serves to remove electrons from said floating gate electrode, thereby altering the control gate threshold voltage of said memory transistor in a second direction opposite said first direction.

Claim 9

A memory device comprising: a plurality of bit lines; a plurality of word lines; bit line addressing means for selecting a desired one of said bit lines and deselecting the remaining bit lines; word line addressing means for selecting a desired one of said word lines and deselecting the remaining word lines; a plurality of memory cells, each uniquely associated with a bit line-word line pair, each said memory cell comprising: a source region; a drain region located apart from said source region and connected to the bit line associated with said memory cell; a channel region located between said source and said drain regions; a floating gate electrode located above said channel region near said source region and not near said drain region, said floating gate electrode separated from said channel by a first dielectric layer; a control gate electrode located above said channel region and said floating gate electrode and separated from said channel region and said floating gate electrode by a second dielectric layer, said control gate electrode being connected to the word line associated with said memory cell; programming means for applying a programming potential between said source region and said word line of a selected memory cell in order to selectively cause a change in the charge stored on said floating gate electrode of said selected memory cell, thereby altering the control gate threshold voltage of said selected memory cell; and a sense amplifier having an input lead connected to said selected bit line and having an output lead for providing an output signal indicative of the data stored in said selected memory cell.

Claim 10

A memory device comprising: a plurality of bit lines; a plurality of word lines; bit line addressing means for selecting a desired one of said bit lines and deselecting the remaining bit lines; word line addressing means for selecting a desired one of said word lines and deselecting the remaining word lines; a plurality of memory cells, each uniquely associated with a bit line-word line pair, each said memory cell comprising: a source region; a drain region located apart from said source region and connected to the bit line associated with said memory cell; a channel region located between said source and said drain regions; a floating gate electrode located above said channel region near said source region and not near said drain region, said floating gate electrode separated from said channel by a first dielectric layer; a control gate electrode located above said channel region and said floating gate electrode and separated from said channel region and said floating gate electrode by a second dielectric layer, said control gate electrode being connected to the word line associated with said memory cell; programming means for applying a programming potential between said source region and said word line of a selected memory cell in order to selectively cause a change in the charge stored on said floating gate electrode of said selected memory cell, thereby altering the control gate threshold voltage of said selected memory cell; and a sense amplifier having an input lead connected to said selected bit line and having an output lead for providing an output signal indicative of the data stored in said selected memory cell.

Claim 11

A structure as in claim 8 wherein said source region is doped to a sufficiently high doping level to increase hot electron injection from that portion of said channel region near said source region to said floating gate during programming.

Claim 12

A structure as in claims 8 or 9 wherein said drain region is doped to a sufficiently low doping level to reduce parasitic drain capacitance.

Claim 13

A structure as in claim 8 wherein said bit line addressing means comprises transistors having breakdown voltages less than the programming voltage applied by said programming means to said source region during programming.

Claim 14

A structure as in claim 8 which further comprises a source field region adjacent at least a portion of said source region not adjacent said channel region, said source field region being not heavily doped, thereby increasing the gated diode breakdown voltage of said source region.

Claim 15

A structure as in claims 8 or 12 which further comprises a drain field region adjacent at least a portion of said drain region not adjacent said channel region, said drain field region being relatively highly doped, thereby increasing the isolation of said drain regions.

Claim 16

A structure as in claim 13 wherein said drain field region serves to provide isolation between adjacent drain regions.

Claim 17

A structure as in claim 8 wherein said programming means serves to add electrons to said floating gate electrode, thereby altering the control gate threshold voltage of said memory transistor in a first direction, and also serves to remove electrons from said floating gate electrode, thereby altering the control gate threshold voltage of said memory transistor in a second direction opposite said first direction.

Claim 18

A structure as in claim 8 further comprising means for precharging said bit lines prior to addressing a selected one of said bit lines for programming a desired one of said memory cells associated with said selected bit line.

Claim 19

A structure as in claim 16 wherein said means for precharging comprises: a precharge source for providing a precharge potential; and a plurality of precharge transistors, each uniquely associated with one of said bit lines, and having a source connected to said bit line, a drain connected to said precharge source, and a control gate connected to means for providing a precharge control signal.

Claim 20

A structure as in claim 16 further comprising means for discharging said selected bit line for programming while leaving all remaining bit lines precharged.

Claim 21

A structure as in claim 18 wherein said means for discharging comprises a transistor having a source connected to said drains of said plurality of precharge transistors, a drain connected to a discharge potential, and a control gate connected to receive a discharge signal.

Claim 22

A structure as in claim 17 wherein said precharge transistors have a breakdown voltage greater than said programming potential.

Claim 23

A structure as in claims 18 or 19 wherein said means for discharging comprises transistors having breakdown voltages greater than said programming potential.