Method and apparatus for sequential programming of a flash EEPROM memory array

Claim 2

A computer system comprising: a central processor; a memory arrangement that further comprises a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, a charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a comparator connected to receive a data word to be programmed into the flash EEPROM memory array for comparing each bit of the data word with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, control circuitry responding to the output signals from the comparator for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump; and a system bus for transferring data and addresses between the central processor and the memory arrangement.

Claim 3

A computer system as claimed in claim 1 in which the control circuitry is a processor which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until the data word has been programmed.

Claim 4

A computer system as claimed in claim 1 in which the selected number is four.

Claim 5

A computer system as claimed in claim 1 in which the control circuitry is an application specific logic circuit which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until yhe data word has been programmed.

Claim 6

A memory arrangement comprising: a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, a charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a comparator connected to receive a data word to be programmed into the flash EEPROM memory array for comparing each bit of the data word with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, and control circuitry responding to the output signals from the comparator for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump.

Claim 7

A memory arrangement comprising: a flash EEPROM memory array including a plurality of floating gate field effect transistor devices, a charge pump for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, a comparator connected to receive a data word to be programmed into the flash EEPROM memory array for comparing each bit of the data word with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, and control circuitry responding to the output signals from the comparator for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump.

Claim 8

A memory arrangement as claimed in claim 5 in which the control circuitry is a processor which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until the data word has been programmed.

Claim 9

A memory arrangement as claimed in claim 5 in which the selected number is four.

Claim 10

A memory arrangement as claimed in claim 5 in which the control circuitry is an application specific logic circuit which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump one group after another until the data word has been programmed.

Claim 11

A computer system comprising: central processing means; means for providing storage of data, further comprising flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, charge pump means for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, means for comparing each bit of a data word to be programmed into the flash EEPROM memory array with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, control means responding to the output signals from the means for comparing for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump; and system bus means for transferring data and addresses between the central processing means and the means for providing storage for data.

Claim 12

A computer system comprising: central processing means; means for providing storage of data, further comprising flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, charge pump means for providing a first positive voltage to be applied to drain terminals of the floating gate field effect transistor devices during a programming operation, means for comparing each bit of a data word to be programmed into the flash EEPROM memory array with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, control means responding to the output signals from the means for comparing for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump; and system bus means for transferring data and addresses between the central processing means and the means for providing storage for data.

Claim 13

A computer system as claimed in claim 9 in which the control means includes processor means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

Claim 14

A computer system as claimed in claim 9 in which the selected number is four.

Claim 15

A computer system as claimed in claim 9 in which the control means includes application specific logic means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

Claim 16

An arrangement for providing storage of data comprising: flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, charge pump means for providing a voltage to be applied to terminals of the floating gate field effect transistor devices during a programming operation, means for comparing each bit of a data word to be programmed into the flash EEPROM memory array with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, and control means responding to the output signals from the means for comparing for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump.

Claim 17

An arrangement for providing storage of data comprising: flash EEPROM memory array means including a plurality of floating gate field effect transistor devices, charge pump means for providing a voltage to be applied to terminals of the floating gate field effect transistor devices during a programming operation, means for comparing each bit of a data word to be programmed into the flash EEPROM memory array with a predetermined voltage in order to generate output signals indicating which bits of the data word need to be programmed, and control means responding to the output signals from the means for comparing for allowing a selected number of the plurality of floating gate field effect transistor devices corresponding to a portion of the bits of the data word that need to be programmed to receive the voltage from the charge pump.

Claim 18

An arrangement for providing storage of data as claimed in claim 13 in which the control means includes processor means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

Claim 19

An arrangement for providing storage of data as claimed in claim 13 in which the selected number is four.

Claim 20

An arrangement for providing storage of data as claimed in claim 13 in which the control means includes application specific logic means which allows groups of the selected number of floating gate field effect transistor devices to be programmed to receive the voltage from the charge pump means one group after another until the data word has been programmed.

Claim 23

A method as claimed in claim 17 which includes, after the step of enabling, the further step of determining whether additional bits exist in the word which are to be programmed but have not yet been programmed.

Claim 24

A method as claimed in claim 17 which includes the further step of verifying that all bits of a selected word have been programmed.