Patent US5430602A successfully refreshed from Google Patents.
US5430602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input protection circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge
Assignee: Samsung Electronics Co Ltd
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Filing: 1993-03-31
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Granted: 1995-07-04
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Expires: 2013-03-31
Abstract
Abstract A circuit is provided for protecting the internal circuit of a semiconductor device from electrostatic discharge (ESD). This circuit includes an input pad for applying an input signal to the internal circuit, a metal line for electrically connecting the input pad and internal circuit. This metal line has at least one RC delay stage caused by inherent parasitic resistances and capacitances. Also, a punch-through element is provided to connect the metal line to a ground voltage terminal disposed between the input pad and a delay stage. Finally, a resistor is used to connect the at least one delay stage to the internal circuit.
Inventors
- 👤 Dae-Je Chin
- 👤 Jong-Hyeon Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 07:57
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/819; H10D89/911
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
102 words
A circuit for protecting an internal circuit of a semiconductor memory device from electrostatic discharge, comprising: an input pad for applying an input signal to said internal circuit; a conduction line for electrically connecting said input pad to said internal circuit, said conduction line having an RC delay stage comprised of inherent parasitic resistance and capacitance parameters; a punch-through element, coupled between said input pad and said RC delay stage, for connecting said conduction line to ground; and a first resistor connected between said RC delay stage and said internal circuit for reducing an RC delay time of said RC delay stage.
Claim 2
Dependent Claim
102 words
A circuit for protecting an internal circuit of a semiconductor memory device from electrostatic discharge, comprising: an input pad for applying an input signal to said internal circuit; a conduction line for electrically connecting said input pad to said internal circuit, said conduction line having an RC delay stage comprised of inherent parasitic resistance and capacitance parameters; a punch-through element, coupled between said input pad and said RC delay stage, for connecting said conduction line to ground; and a first resistor connected between said RC delay stage and said internal circuit for reducing an RC delay time of said RC delay stage.
Claim 3
Dependent Claim
25 words
A circuit as defined in claim 1, wherein said first resistor is connected to a gate of a MOS transistor provided in said internal circuit.
Claim 4
Dependent Claim
20 words
A circuit as defined in claim 2, wherein said first resistor is a diffusion region comprised of a conductive material.
Claim 5
Dependent Claim
37 words
A circuit as defined in claim 1, further comprising a second resistor connected in series with a clamping circuit, cascadedly connected between said input pad and said RC delay stage, for connecting said conduction line to ground.
Claim 6
Dependent Claim
118 words
A circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising: an input pad for applying an input signal to said internal circuit; a conduction line for electrically connecting said input pad to said internal circuit, said conduction line having an RC delay stage comprised of inherent parasitic resistance and capacitance parameters; a punch-through element, coupled between said input pad and said RC delay stage, for connecting said conduction line to ground; a first resistor for connecting said RC delay stage to said internal circuit; and a second resistor connected in series with a clamping circuit, cascadedly connected between said input pad and said RC delay stage, for connecting said conduction line to ground.
Claim 7
Dependent Claim
118 words
A circuit for protecting an internal circuit of a semiconductor device from electrostatic discharge, comprising: an input pad for applying an input signal to said internal circuit; a conduction line for electrically connecting said input pad to said internal circuit, said conduction line having an RC delay stage comprised of inherent parasitic resistance and capacitance parameters; a punch-through element, coupled between said input pad and said RC delay stage, for connecting said conduction line to ground; a first resistor for connecting said RC delay stage to said internal circuit; and a second resistor connected in series with a clamping circuit, cascadedly connected between said input pad and said RC delay stage, for connecting said conduction line to ground.
Claim 8
Dependent Claim
25 words
A circuit as defined in claim 5, wherein said first resistor is connected to a gate of a MOS transistor provided in said internal circuit.
Claim 9
Dependent Claim
20 words
A circuit as defined in claim 6, wherein said first resistor is a diffusion region comprised of a conductive material.
Claim 10
Dependent Claim
112 words
A semiconductor device comprising: an input pad; an internal circuit; a conduction line for electrically connecting said input pad to said internal circuit, said conduction line having an RC delay stage comprised of inherent parasitic resistance and capacitance parameters; a punch-through element, coupled between said input pad and said RC delay stage, for connecting said conduction line to ground; a first resistor connected between said RC delay stage and said internal circuit for reducing an RC delay time of said RC delay stage; and a second resistor connected in series with a clamping circuit, cascadedly connected between said input pad and said RC delay stage, for connecting said conduction line to ground.
Claim 11
Dependent Claim
112 words
A semiconductor device comprising: an input pad; an internal circuit; a conduction line for electrically connecting said input pad to said internal circuit, said conduction line having an RC delay stage comprised of inherent parasitic resistance and capacitance parameters; a punch-through element, coupled between said input pad and said RC delay stage, for connecting said conduction line to ground; a first resistor connected between said RC delay stage and said internal circuit for reducing an RC delay time of said RC delay stage; and a second resistor connected in series with a clamping circuit, cascadedly connected between said input pad and said RC delay stage, for connecting said conduction line to ground.
Claim 12
Dependent Claim
26 words
A semiconductor device as defined in claim 8, wherein said first resistor is connected to a gate of a MOS transistor provided in said internal circuit.
Claim 13
Dependent Claim
21 words
A semiconductor device as defined in claim 9, wherein said first resistor is a diffusion region comprised of a conductive material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1998-07-03 | 1999-01-02 | 1999-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-03 | 2003-01-02 | 2003-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-03 | 2007-01-02 | 2007-07-04 | $7700.00 | Window Closed / Lapsed |